Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits

Jul 16, 2026

Pre-Charge Half Buffer (PCHB) is a promising asynchronous design approach for harsh-environment operation, yet its soft-error behavior has remained insufficiently studied. This paper develops a systematic characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework extracts polarity-dependent critical charge at internal nodes, then vulnerability nodes are identified via extensive simulation. Four mitigation strategies are implemented and evaluated across representative cells with resilience-overhead comparisons in delay, energy, and area, enabling architecture-specific hardening guidelines.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages6

Reading Time15 min

Introduction

Static PCHB framework

Soft-error modeling and vulnerability analysis

Mitigation schemes

Simulation results and comparative evaluation

Conclusion

Soft-Error Characterization and Hardening Trade-offsin Static PCHB Asynchronous Circuits Ramya Karri, Srija Rasoori, and Ashiq A. Sakib Dept. of Electrical and Computer Engineering Southern Illinois University Edwardsville, Edwardsville, IL, USA {rkarri; srasoor; [asakib}@siue.edu](asakib}@siue.edu) Abstract—Pre-Charge Half Buffer (PCHB) is a promising asynchronous digital design paradigm for harsh-environment operation; however, its soft-error characteristics remain largely unexplored. This paper presents a systematic soft-error characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework is developed to extract polarity-dependent critical charge at internal nodes. Vulnerability nodes are identified based on extensive simulation. Four mitigation strategies, double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, are implemented and evaluated across five representative PCHB cells. Comprehensive resilience-overhead comparisons in delay, energy, and area are reported, leading to architecture-specific hardening guidelines for robust static PCHB design. Keywords—Pre-charge half buffer, asynchronous design, softerror, radiation-hardening, quasi-delay-insensitive (QDI) I. INTRODUCTION Digital integrated circuits (ICs) designed for operation under extreme environments are essential to applications of national importance, including space exploration, deep-sea missions, and defense surveillance systems. Ensuring dependable operation under such conditions, however, remains a significant challenge. Aggressive device and supply voltage scaling increase susceptibility to radiation, electromagnetic interference (EMI), and other noise sources [1] . Radiation-induced soft errors, known as single-event upsets (SEUs), occur when high-energy particles strike sensitive nodes, generating transient current pulses that may either dissipate or get latched and propagate through the logic network, causing unintended state changes [2] . The risk of SEUs is particularly pronounced in conventional clock-driven synchronous circuits at advanced technology nodes, where reduced supply voltages and tighter timing margins amplify sensitivity to process, voltage, and temperature (PVT) variations. Such transient faults can disrupt timing relationships, cause loss of synchronization, and ultimately lead to functional failure. In contrast, quasi-delay-insensitive (QDI) asynchronous (clockless) architectures mitigate several timingrelated vulnerabilities due to their insensitivity to precise delay assumptions and can offer improve tolerance to EMI and PVT variations, making them a compelling alternative for harshenvironment operation [3, 4], although they are not entirely immune to SEU effects [5] . Null Convention Logic (NCL) [6] and Pre-Charge Half Buffers (PCHB) [7] are two major QDI paradigms. Among these, NCL has historically received greater research attention. This trend is largely attributable to its synchronous-like framework, which can leverage existing computer-aided design (CAD) infrastructures with relatively minor adaptation. Consequently, prior investigations into soft-error resilience and architectural hardening in QDI systems have focused predominantly on NCL-based implementations, including nodelevel fault characterization, Schmitt-trigger-based filtering, and duplication-based redundancy techniques [3, 8-10] . Although NCL and PCHB have similarities, their framework, evaluation, and holding mechanisms differ substantially. For instance, static PCHB circuits employ a stateretention mechanism based on internal regenerative feedback rather than threshold-based input consensus in NCL. This structural distinction alters transient fault dynamics, node-level sensitivity, and protocol-level error behavior. As a result, resilience characteristics and mitigation assumptions established for NCL ma

FAQs

What problem does the paper address about static PCHB circuits?

It addresses the lack of systematic study on static PCHB soft-error characteristics, including critical vulnerability points and the resulting hardening trade-offs.

How is soft-error susceptibility quantified in the proposed methodology?

A transistor-level fault-injection framework captures polarity-dependent critical charge at internal nodes, and extensive simulation is used to identify dominant vulnerability nodes.

Which mitigation strategies are evaluated, and what impact metrics are compared?

The paper evaluates double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, comparing their effects on critical charge, area, propagation delay, and switching energy.

Jul 16, 2026

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