ARMOR-IMC: Adaptive Resource Mapping for Operational Robustness via Secure In-Memory Computing

Jul 16, 2026

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In-memory computing (IMC) reduces the data-movement overhead of traditional architectures for energy-efficient deep neural network (DNN) processing, especially with emerging SOT-MTJ based devices. This shift, however, creates dual risks: process variation (PV) that triggers reliability loss and fault injection susceptibility, and data-dependent power side-channel attacks (SCAs) that threaten confidentiality. ARMOR-IMC introduces a posttraining framework that hardens analog IMC accelerators against both threats without retraining, using VIS and LPI to guide adaptive mapping and quantify leakage-driven signal-noise degradation.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages4

Reading Time10 min

Introduction

In-Memory Computing (IMC) and Process Variation

Background and Motivation

Threat Model and Security Risks

ARMOR-IMC Framework Overview

Variation Impact Score (VIS)

Leakage Per Inference (LPI)

ARMOR-IMC: Adaptive Resource Mapping for Operational Robustness via Secure In-Memory Computing Muhtasim Alam Chowdhury∗ , Ramtin Zand†, Soheil Salehi∗ †Department of Computer Science and Engineering, University of South Carolina, Columbia, SC, USA ∗ Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA {mmc7, [ssalehi](ssalehi}@arizona.edu)[}](ssalehi}@arizona.edu)[@arizona.edu](ssalehi}@arizona.edu)∗ , [ramtin@cse.sc.edu](ramtin@cse.sc.edu)† arXiv :2607 . 10938v 1 [ cs .CR] 12 Jul 2026 Abstract—The massive data-movement overhead in traditional architectures has led to the adoption of In-Memory Computing (IMC) for energy-efficient Deep Neural Network (DNN) processing. By leveraging emerging devices like Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), IMC bypasses the“memory wall” and reduces leakage power inherent in traditional CMOS. However, this shift introduces dual hardware threats: manufacturing Process Variation (PV) degrades reliability and increases vulnerability to fault injection, while power SideChannel Attacks (SCAs) compromise security. Existing defenses address these threats in isolation. This work presents a posttraining framework that simultaneously hardens analog IMC accelerators against both threats without retraining the model. Implemented in the IMAC-Sim simulator, our approach uses the proposed Variation Impact Score (VIS) to guide the mapping of Fault Observation Windows (FOWs) and introduces the Leakage Per Inference (LPI) metric to quantify input-dependent power variability under stochastic injection and the resulting reduction in effective signal-to-noise ratio. Experiments show that PVinduced faults can degrade accuracy by over 50%, while our method restores near-baseline accuracy and mitigates the threat of correlation-based power analysis attacks. Keywords—Secure In-Memory Computing, Robust AI Accelerators, Emerging Devices, Side-Channel Mitigation I. INTRODUCTION Deep Neural Networks (DNNs) are now integral to missioncritical systems, placing immense strain on conventional hardware. To overcome the resulting von Neumann bottleneck, the underlying hardware is shifting towards In-Memory Computing (IMC) architectures that leverage emerging devices like Spin-Orbit Torque Magnetic Tunnel Junction (SOT-MTJ) based Magnetic Random Access Memories (MRAMs) [1] . However, this transition introduces significant hardware security and reliability challenges that threaten the integrity and confidentiality of AI workloads. The first major threat is reliability degradation caused by manufacturing Process Variation (PV) . Our prior work demonstrated that subtle, adversarial, or unintentional variations in physical parameters, such as the SOT-MTJ device’s oxide thickness (tox ), can alter its resistive states, inducing systemic bit-flips in the MRAM weight arrays that significantly degrade the inference accuracy of the deployed DNN model [2], [3] . The second major threat is physical Side-Channel Attacks (SCAs) . It is wellestablished that DNN accelerators are vulnerable to attacks where an adversary with physical proximity measures the device’s power consumption to infer secret data. Since the power consumed by a circuit is data-dependent, attackers can Fig. 1. Overview of the ARMOR-IMC framework, illustrating the overall scope and highlighting the dual-metric analysis and adaptive mapping flow for improving both reliability and side-channel resilience in IMC accelerators. leverage statistical techniques such as Correlation Power Analysis (CPA) and Differential Power Analysis (DPA) to recover the secret parameters of the model, potentially compromising its Intellectual Property (IP) [4] . While some defenses exist, they typically address these reliability and security threatsin isolation, leaving a critical gap where a system hardened against one threat remains vulnerable to the other. To address this gap, we propose ARMOR-IMC, illustrated in Fig

FAQs

What security and reliability threats does ARMOR-IMC address in analog IMC accelerators?

ARMOR-IMC simultaneously targets process-variation-induced reliability degradation and physical side-channel attacks that exploit input-dependent power consumption.

How does ARMOR-IMC reduce the need for costly model retraining?

It is implemented as a posttraining framework that hardens the analog IMC accelerators without retraining the DNN model.

What are VIS and LPI, and what roles do they play in the framework?

Variation Impact Score (VIS) guides mapping decisions by quantifying reliability risk from fault injection over Fault Observation Windows (FOWs). Leakage Per Inference (LPI) measures input-dependent power variability and the resulting reduction in effective signal-to-noise ratio under stochastic injection.

Jul 16, 2026

Upload by Skyler