Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques

Jul 16, 2026

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3D full-domain 3 nm gate-all-around (GAA) FET SRAM cells are investigated with TCAD simulations to evaluate self-heating and radiation hardness under multiple substrate isolation schemes. Along with bottom dielectric isolation (BDI) implementations, including SD-BDI and a punch-through stopper (PTS), a novel channel-BDI (C-BDI) is proposed to permit S/D-to-substrate connectivity. Results show negligible self-heating increase from BDI, minimal IOFF rise in CBDI without PTS, and robust SNM under single-event upset even with 20 nm underlap.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages4

Reading Time10 min

Introduction

TCAD simulations and results

BDI implementations and SRAM design

Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques Albert Lu San Jose State University San Jose, California, USA [albert.lu@sjsu.edu](albert.lu@sjsu.edu) Junipero Verbeke San Jose State University San Jose, California, USA [junipero.verbeke@sjsu.edu](junipero.verbeke@sjsu.edu) Phil Oldiges Sandia National Laboratories New Mexico, USA[pjoldig@sandia.gov](pjoldig@sandia.gov) Reza Arghavani Sandia National Laboratories New Mexico, USA[rarghav@sandia.gov](rarghav@sandia.gov) Hiu Yung Wong∗ San Jose State University San Jose, California, USA [hiuyung.wong@sjsu.edu](hiuyung.wong@sjsu.edu) arXiv :2607 .05789v 1 [ cs .ET] 7 Jul 2026 Abstract—In this work, 3D full-domain 3 nm gate-all-around field-effect transistor (GAA-FET) static random access memories (SRAMs) with various substrate isolation techniques are simulated using Technology Computer-Aided Design (TCAD). In addition to the traditional bottom dielectric isolation (BDI), which isolates the source/drain (S/D) from the substrate (dubbed SDBDI), and the punch-through stopper (PTS), a novel channel-BDI (C-BDI) is proposed, allowing S/D-to-substrate connection. The self-heating effect and radiation hardness due to various isolation techniques are studied. It is found that, firstly, the increase in self-heating due to BDI is negligible. Secondly, in the novel CBDI, even without PTS, the increase in leakage current IOFF is minimal. Thirdly, for SD-BDI with underlap (to minimize stress relaxation), while IOFF increases, the static noise margin (SNM) remains unchanged and robust against single-event upset (SEU) even if the underlap is as much as 20 nm. Finally, all structures are immune to the alpha-particle SEU, and BDI enhances the radiation hardness substantially. Moreover, radiation hardness is insensitive to BDI thickness. Index Terms—Bottom Dielectric Isolation (BDI), GAA-FET, Radiation Hardness, SRAM, Self-Heating, TCAD I. INTRODUCTION As semiconductor scaling progresses into the sub-5 nm regime, GAA-FETs have emerged as the leading architectural candidate to replace FinFETs [1] . By fully surrounding the channel with the gate, GAA-FETs offer superior electrostatic control, reduced short-channel effects, and improved drive current. Despite these advantages, the substrate subchannel is highly prone to parasitic leakage. To mitigate this subchannel leakage, several substrate isolation techniques have been studied in the literature, such as PTS and BDI [2] . PTS uses a relatively heavily doped layer beneath the channel and source/drain (S/D) to prevent substrate leakage. It is doped with the opposite type as the S/D. In the literature, BDI usually refers to an oxide layer used to isolate the S/D from the substrate and has two forms that are often studied [3]–[5] . “Partial” BDI is often defined as Fig. 1. Cross-sections of the GAA-FETs under study. Both structures mayor may not have PTS. tunder , text, and h are BDI parameters adjusted in this study. (a) GAA-FET with SD-BDI. The BDI is under the S/D. A Structure with PTS and SD-BDI underlap is shown. The substrate leakage path is indicated. (b) GAA with C-BDI, where BDI is under the channel. when the oxide layer is placed only under the S/D (Fig. 1a, where it also has a PTS) . “Full” BDI is when the oxide layer is placed under the S/D and channel as well (where the subchannel is at) . PTS has the disadvantages of being more prone to process variations and higher parasitic capacitances. However, PTS allows a direct connection from the S/D to enable stress formation in the S/D and has the potential to reduce self-heating. BDI reduces subthreshold leakage and parasitic capacitance due to the oxide layer. BDI does not use doping, so it also allows for less consideration to process variations due to doping. Furthermore, BDI is also found tobe beneficial for radiation hardness [4] . However, BDI has the disadvantage of severing the conn

FAQs

What simulation method and device scope are used to study the SRAMs?

The work uses full-domain 3D TCAD simulations with Sentaurus (SDevice and SProcess) on 3 nm GAA-FET SRAMs. The approach is intended to capture layout effects and analyze both self-heating and radiation hardness.

How do SD-BDI and C-BDI differ in substrate isolation and electrical connectivity?

SD-BDI places the BDI under the source/drain, with an underlap parameter that controls electrical connection to the substrate. C-BDI is a channel-BDI approach where BDI is positioned under the channel, allowing S/D-to-substrate connection and evaluating behavior even without PTS.

What are the key findings regarding self-heating, leakage, and radiation hardness?

Self-heating increase due to BDI is negligible, and in C-BDI the IOFF increase is minimal even without PTS. For SD-BDI with underlap, static noise margin stays unchanged and remains robust against single-event upset, while all structures are immune to alpha-particle SEU and BDI substantially improves radiation hardness with insensitivity to BDI thickness.

Jul 16, 2026

Upload by Levi