SABLE An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

Jul 16, 2026

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Large language models can propose circuit-sizing decisions, yet industrial analog design flows cannot expose foundry PDK content, proprietary schematic details, absolute simulation paths, or license-bound tool state to a cloud endpoint. SABLE (Safe Analog Boundary for LLM-driven EDA) provides an NDA-safe closed-loop framework using Cadence Virtuoso, Maestro, and Spectre. It returns only scrubbed topology intent, numeric metrics, operating-point summaries, and scoped writeback status, enforced by a threat model, whitelisted SKILL entry points, per-path scrubbing, and a strict JSON action contract with stop conditions. Evaluations on two real closed-loop tasks show higher pass rates when tool discipline and specification repair are required.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages21

Reading Time53 min

AccessFree to download

Introduction

NDA-safe closed-loop framework overview

Threat model and boundary enforcement

Evaluation setup and tasks

Results and ablation insights

arXiv :2607 .0370 1v 1 [ cs .AR] 4 Jul 2026 SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows XUNQI LI, University of Minnesota, Twin Cities, US CHRIS H. KIM, University of Minnesota, Twin Cities, US Large language models (LLMs) can propose circuit-sizing decisions, but industrial analog design flows cannot simply expose foundry process-design-kit (PDK) content, proprietary schematic details, absolute simulation paths, or license-bound tool state to a cloud endpoint. This paper presents SABLE (Safe Analog Boundary for LLM-driven EDA), an NDA-safe closed-loop framework that lets LLMs optimize analog circuits through Cadence Virtuoso, Maestro, and Spectre while returning only scrubbed topology intent, numeric simulation metrics, operating-point summaries, and scoped writeback status. We use “NDA-safe” to mean enforcement under a stated curious-but-passive cloud-provider threat model, not a formal non-interference proof. The framework combines an explicit threat model for the cloud-LLM boundary, a whitelist of 28 scoped SKILL entry points, PDK/path/model scrubbing on every return path, structured Maestro setup and writeback recipes, a strict JSON action contract with six machine-checked stop conditions, and best-so-far state preservation. We evaluate eleven LLM checkpoints from the same documented reset state on two real closed-loop tasks, both run as process–voltage–temperature (PVT) sign-offs across the same three corners: a 20 GHz LC-VCO tuning-curve optimization task and a differential two-stage op-amp optimization task. On the LC-VCO task, 7 of 11 models pass; on the harder op-amp task—where every metric must hold at the worst of three cornersand a phase-margin gate rejects unstable high-gain points—4 of 11 models pass within the 15-iteration budget. Single-checkpoint feedback-path ablations show that removing individual sanitized feedback channels either silently weakens the specification or measurably degrades the search. The results show that model quality differs sharply once the loop requires tool discipline, bias reasoning, and specification repair, and that an NDA-safe EDA boundary can still provide enough sanitized feedback for successful analog circuit optimization. Additional Key Words and Phrases: LLM agents, analog circuit optimization, EDA automation, Cadence Virtuoso, Maestro, Spectre, NDA-safe design automation, LLM4EDA 1 Introduction LLM-driven EDA loops are useful only when the tool boundary is as carefully engineered asthe prompt. Recent digital, HLS, and full-flow EDA agents use compiler, synthesis, place-androute, or simulation feedback to refine LLM-generated artifacts [4, 5, 13, 14, 19, 20] . Analog circuit optimization is a natural next target because SPICE simulation provides a direct numerical oracle. However, the analog case introduces a deployment constraint that is not a minor implementation detail: a real foundry-bound Virtuoso flow contains PDK model cards, proprietary cell names, private schematic hierarchy, absolute host paths, and license-bound simulation state that cannot be sent to a cloud LLM. Existing analog LLM work has made rapid progress on code generation, topology synthesis, sizing, testbench construction, and benchmark design [1, 3, 6–10, 12, 16–18, 22–24]. The missing Authors’ Contact Information: Xunqi Li, University of Minnesota, Twin Cities, Minneapolis, US, [li001674@umn.edu](li001674@umn.edu); Chris H. Kim, University of Minnesota, Twin Cities, Minneapolis, US, [chriskim@umn.edu](chriskim@umn.edu). Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To cop

FAQs

What problem does SABLE solve for using LLMs in industrial analog EDA flows?

It enables LLM-driven optimization without leaking NDA-bound information such as PDK content, proprietary schematic hierarchy, absolute simulator paths, or license-bound tool state to a cloud endpoint.

How does SABLE keep the cloud-LLM boundary NDA-safe?

SABLE enforces a stated curious-but-passive cloud-provider threat model, scrubs sensitive artifacts on return paths, limits interactions through a whitelist of scoped SKILL entry points, and uses a strict JSON action contract with machine-checked stop conditions.

What tasks and outcomes are evaluated in the paper?

The framework is tested on two closed-loop analog optimization tasks: 20 GHz LC-VCO tuning-curve optimization and differential two-stage op-amp optimization across the same PVT sign-off corners. Pass rates are reported (7/11 for LC-VCO and 4/11 for the op-amp task within a 15-iteration budget), with ablations showing that removing sanitized feedback channels harms search or specifications.

Jul 16, 2026

Upload by Aria