Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip

Jul 16, 2026

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As many-core SoCs scale, AXI4 Networks-on-Chip must sustain high memory bandwidth without deadlocks, even when routing is deadlock-free. AXI4 endpoints can introduce protocol-level circular waits by coupling read and write traffic at the network boundary. Separating traffic classes avoids these dependencies, but multiplane designs duplicate wide links while conventional virtual-channel routers add control, area, and timing overhead. This work evaluates four deadlock-free AXI4 separation schemes and proposes Preemptive VCs for lightweight deadlock freedom with improved resource efficiency.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages5

Reading Time13 min

AccessFree to download

Introduction

Problem: protocol-level deadlocks in AXI4 NoCs

Background: decoupling traffic with VCs and multiplane

Motivation: wide-link and reliability constraints

Proposed solution and contributions

Preemptive VCs concept

Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip Lorenzo Leone 1, Luca Colagrande 1, Luca Benini 1,2 1 ETH Zürich, Zürich, Switzerland, 2 Università di Bologna, Bologna, Italy {lleone, colluca, [lbenini}@iis.ee.ethz.ch](lbenini}@iis.ee.ethz.ch) 1 Jul 2026 Abstract—As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, protocol-level dependencies between read and write traffic can create circular waits at the network endpoints, even when the routing algorithm itself is deadlock-free. Decoupling these traffic classes avoids such dependencies, but exposes a key implementation trade-off: multiplane NoCs duplicate wide physical links and increase routing pressure, whereas conventional Virtual Channel (VC) routers add substantial control complexity, area, and timing overhead. This work revisits this trade-off for modern wide-link NoCs. We evaluate four deadlock-free AXI4 traffic-class separation schemes: a multiplane baseline and three lightweight VC-based designs. Among these designs, we propose arXiv :2607 .01430v1 As many-core SoCs continue to scale [1], the memory traffic generated by large numbers of processing elements increases sharply, making high-bandwidth and scalable NoCs essential for sustaining performance. At the same time, providing industry-standard AXI4 [2] interfaces at the network boundaries remains critical for seamless integration of existing IPs, usually designed with AXI4 initiator and/or target interfaces [3]–[5] . Deadlock freedom remains a central requirement in NoCs, both at the routing and protocol levels [6]–[8] . Endpoint behavior in AXI4-based systems creates protocol dependencies that are invisible to the routing algorithm itself. Thus, even when deterministic XY routing is employed, protocol-level deadlocks may still arise if AXI4-capable endpoints internally couple read and write transactions [7] . Fig. 1a illustrates a representative case in which a DMA engine (AXI4 initiator) issues a read burst request to a remote memory . As the read data returns, each AXI4 beat is immediately forwarded into a write burst directed to a local L1 Scratch-Pad Memory (SPM) (AXI4 target) through the AXI4 crossbar . If, before the DMA completes, an external initiator issues a write burst to the same L1 SPM , its request may occupy the local NoC link . The DMA can then no longer make forward progress on the readresponse path , and a protocol-level circular wait arises at the network endpoint, stalling the entire system. More generally, the challenge of protocol- or message-dependent deadlocks caused by the interaction between NoCs and endpoint protocols has long been recognized in the literature [7]–[9] . To eliminate protocol-level deadlocks without constraining endpoint behav- Fig. 1: a) Deadlock scenario: all links are blocked (red arrowheads) or starved (red tails); b) Router design space. ior, AXI4 read and write channels must also be decoupled so that they cannot block one another on the same NoC link. One solution is to use VCs [10], [11] . As shown in Fig. 2a, VCs provide separate buffers for different data streams while preserving a shared physical link. In our case, AXI4 read and write transactions can be assigned to distinct buffers, so that returning read data and incoming write data no longer compete for the same downstream path in the local interconnect. A flit may occupy the shared link only if the corresponding downstream buffer has free space, ensuring that the link is released in the next cycle. A second solution is the multiplane approach [12], [13], which assigns different traffic classes to separate physical links, thereby avoiding inter-class blocking on shared links. Prior work has established the conventional view that VCs are more complex than multiplane designs [13]–[15], largely because earlier studies consi

FAQs

Why can AXI4 Networks-on-Chip deadlock even with deadlock-free routing algorithms?

Because AXI4 endpoint behavior can create protocol-level dependencies between read and write traffic, leading to circular waits at network endpoints independent of routing.

How does traffic-class separation prevent protocol-level deadlocks?

By decoupling AXI4 read and write channels so they cannot block each other on the same NoC link, eliminating circular wait conditions.

What trade-off exists between multiplane designs and virtual-channel routers for deadlock-free AXI4 separation?

Multiplane designs avoid inter-class blocking by duplicating physical links but increase routing pressure, while conventional VC routers preserve shared links but add substantial control complexity, area, and timing overhead.

Jul 16, 2026

Upload by Hazel