HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA

Jul 16, 2026

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Network-on-Chip (NoC) interconnects face a persistent trade-off between latency, area cost, and congestion management. HyNoC introduces a hybrid open-source NoC architecture for distributed VLIW computing on FPGA, combining circuit-switch path establishment with wormhole-style data transfer. Source routing encodes complete paths in packet headers to achieve deterministic low-latency communication and software-level hotspot avoidance without virtual-channel area overhead. A router design adds a parallel round-robin arbiter, fixed grant latency, independent clock domains, and unicast/multicast support. Verilator co-simulation validates per-hop latency and quadrant isolation, and RTL is released under CERN-OHL-Pv2.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages14

Reading Time35 min

AccessFree to download

Introduction

Switching Strategies

Related Work

Switching Strategies

HyNoC Architecture

Hybrid Switching Model

Target Application Domain

Implementation Details

Simulation Results

Conclusion

HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA Christophe Clienti Independent Researcher [christophe.clienti@mines-paris.org](christophe.clienti@mines-paris.org) [https://github.com/cclienti/verilog-ip/tree/master/hw/network/hynoc](https://github.com/cclienti/verilog-ip/tree/master/hw/network/hynoc) arXiv :2607 .02729v 1 [ cs .AR] 2 Jul 2026 Abstract—Network-on-Chip (NoC) architectures have become the standard interconnect fabric for many-core systems, yet most proposals face a fundamental trade-off between latency, area, and congestion management. This paper presents HyNoC (Hybrid Network-on-Chip), an open-source NoC architecture that combines circuit-switch path establishment with wormhole data transfer, targeting distributed computing systems built around VLIW processor cores on FPGA. HyNoC employs source routing, where the complete path through the network is encoded in the packet header by thesender or statically at compile time, enabling both deterministic low-latency transfers and software-level hotspot avoidance without the area overhead of virtual channels. The router features a parallel round-robin arbiter (PRRA) with fixed grant latency, per-port independent clock domains, and support for both unicastand multicast routing. We discuss the design rationale, the hybrid switching model, and positioning relative to prior NoC art, and argue that a richer topology combined with compiler-assisted static routing is a competitive alternative to virtual channels for FPGA-based distributed VLIW systems. Verilator co-simulation measures the deterministic per-hop latency and benchmarks the design at LLaMA 3 8BFFN up-projection scale: a four-master quadrant configuration partitions the mesh into traffic-isolated quadrants with zero crossquadrant link traffic, yielding a 5 × throughput improvement over a single master. The complete RTL implementation is available as open-source hardware under the CERN-OHL-Pv2 license. Index Terms—Network-on-Chip, FPGA, source routing, wormhole switching, circuit switching, VLIW, parallel round-robin arbiter, open-source hardware. I. INTRODUCTION As the number of processing elements integrated on a single chip increases, scalable on-chip communication becomes a firstclass design concern. Network-on-Chip (NoC) architectures have emerged as the standard answer to this challenge, replacing shared buses and point-to-point links with a structured, packetswitched interconnect fabric [1] . Existing NoC designs span a broad design space. Wormhole switching minimizes buffering by forwarding flits as soon asthe header is decoded, but exposes the network to head-of-line blocking. Virtual channels (VCs) were introduced to mitigate this blocking [2], at the cost of duplicated buffers that can represent the dominant area contribution of a router [3] . Circuit switching provides fully dedicated, contention-free paths but requires path reservation before any data can flow. HyNoC takes a different approach: it combines the pathdedication property of circuit switching—through a sourcerouted request/grant handshake at each hop—with the flit-level, FIFO-backed flow control of wormhole switching. This hybrid model is particularly well suited to FPGA targets, where block RAMs used as FIFOs are scarce resources, and to distributed VLIW computing workloads, where communication patterns are largely known at compile time and can therefore be routed statically to avoid congestion. Originally inspired by the Hermes NoC [4], HyNoC departs significantly from its ancestor by introducing distributed arbitration, relative source routing with multicast support, perport asynchronous clock domains, and a parallel round-robin arbiter that grants requests in a one or two cycles. The contributions of this paper are: • A precise characterization of HyNoC’s hybrid switching model and its implications for latency and area; • A discussion of static route manage

FAQs

What problem does HyNoC address in network-on-chip designs?

It targets the common NoC trade-off among latency, router area, and congestion management, which typically forces designers to compromise on one factor.

How does HyNoC combine circuit switching and wormhole switching?

HyNoC uses source-routed request/grant handshakes at each hop for path dedication (circuit-switch property) while using flit-level FIFO-backed flow control for wormhole-style transfer.

Why avoid virtual channels in HyNoC, and what enables hotspot control?

HyNoC aims to avoid the duplicated buffering area cost of virtual channels by relying on compiler-assisted static routing and deterministic source routing, enabling software-level hotspot avoidance.

Jul 16, 2026

Upload by Maeve