Design Space Exploration for Edge Machine Learning Featured by MathWorks - FPGA DL Processor - A Survey

Sep 17, 2026

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This paper proposes a design space exploration for edge machine learning by leveraging the novel MathWorks FPGA Deep Learning Processor IP in the HDL Deep Learning toolbox. It targets the growing need for real-time, low-latency inference close to the data source. The HDL Deep Learning toolbox enables flexible deployment of deep learning models on FPGAs for embedded IoT. The study analyzes how parallel processing elements affect performance and resource utilization, balancing accuracy, speed, energy efficiency, and hardware resources. Experiments run on the AMD-Xilinx ZC706 board using compatible CNNs from the toolbox.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages22

Reading Time55 min

AccessFree to download

Introduction

Paper Organization

Received 21 November 2023, accepted 8 January 2024, date of publication 10 January 2024, date of current version 22 January 2024. Digital Object Identifier 10.1109/ACCESS.2024.3352266 Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey STEFANO BERTAZZONI, LORENZO CANESE, GIAN CARLO CARDARILLI,(Life Member, IEEE), LUCA DI NUNZIO,(Member, IEEE), ROCCO FAZZOLARI, MARCO RE,(Member, IEEE), AND SERGIO SPANÒ Department of Electronic Engineering, Tor Vergata University of Rome, 00133 Rome, Italy Corresponding author: Sergio Spanò ([spano@ing.uniroma2.it](spano@ing.uniroma2.it)) This work has been supported by the Spoke 1 FutureHPC & BigData of the Italian Research Center on High-Performance Computing, Big Data and Quantum Computing (ICSC) funded by Ministero dell’Università e della Ricerca (MUR) Mission 4-Next Generation EU. ABSTRACT This paper proposes a Design Space Exploration for Edge machine learning through the utilization of the novel MathWorks FPGA Deep Learning Processor IP, featured in the HDL Deep Learning toolbox. With the ever-increasing demand for real-time machine learning applications, there is a critical need for efficient and low-latency hardware solutions that can operate at the edge of the network, in close proximity to the data source. The HDL Deep Learning toolbox provides a flexible and customizable platform for deploying deep learning models on FPGAs, enabling effective inference acceleration for embedded IoT applications. In this study, our primary focus lies in investigating the impact of parallel processing elements on the performance and resource utilization of the FPGA-based processor. By analyzing the trade-offs between accuracy, speed, energy efficiency, and hardware resource utilization, we aim to gain valuable insights into making optimal design choices for FPGA-based implementations. Our evaluation is conducted on the AMD-Xilinx ZC706 development board, which serves as the target device for our experiments. We consider all the compatible Convolutional Neural Networks available within the HDL Deep Learning toolbox to comprehensively assess the performances. INDEX TERMS Convolutional neural networks, deep learning, design space exploration, edge machine learning, embedded, FPGA, IoT, machine learning. I. INTRODUCTION The deployment of Deep Learning networks on FPGA isone of the most trending topics of recent years’ literature, especially if it is targeted to Edge Machine Learning applications [1],[2],[3],[4],[5] . Due to the complexity of meeting the different requirements in such scenarios (e.g. Embedded IoT), several researchers highlighted the need to perform an extensive Design Space Exploration (DSE) taking into account both the target device and network to be implemented [6],[7],[8],[9],[10] . Moreover, different works tried to help the designers The associate editor coordinating the review of this manuscript and approving it for publication was Tony Thomas. proposing some kind of automation for DSE analysis on FPGA-oriented deep learning applications [11], [12],[13],[14] . According to Pham et al. [15], the most complex challenge for the acceleration of CNNs on hardware is the Design Space Exploration phase. This concept has been successively extended by Pham to FPGA devices [16] by proposing the graph in Fig. 1. The time to design the network is the easiest requirement, mainly due to the plethora of off-the-shelf tools to build, train, and validate a CNN. A medium effort is required when the developer has to deal with the limited amount of memory and the relative clock frequencies of FPGAs. The data communication overhead to exchange the data with the 􀀊 2024 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. 9418 For more information, see [https://creativecommons.org/licenses/by-nc-nd/4.0/ VOLUME 12, 2024](https://creativecommons.org/licenses/by-nc-nd/4.0

FAQs

Which evaluation trade-offs and processor factors are analyzed?

The work focuses on the impact of parallel processing elements and studies trade-offs among accuracy, speed, energy efficiency, and FPGA hardware resource utilization.

Sep 17, 2026

Uploaded by Ivy