CMAX-CAMEL Coarse to Fine Adaptive Memory Efficient Low Power Edge Processor for Contrast Maximization

Jul 16, 2026

Contrast maximization (CMAX) provides a geometric approach to event-based motion estimation, yet its iterative warp-and-accumulate pipeline causes input-dependent computation and frequent memory traffic, making real-time, low-power edge deployment difficult. CMAX-CAMEL introduces a coarse-to-fine adaptive, memory-centric processor that adjusts execution stages based on observed event distribution. Banked parallel memory maintains throughput, while subsampling-coupled accumulation reduces memory accesses. FPGA results at 200 MHz show up to 19% higher accuracy, 53.3% lower latency, 42% fewer effective memory accesses, and 52.2% less system energy including adaptation overhead.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages8

Reading Time20 min

Introduction

Event-based motion estimation and CMAX

Coarse-to-fine execution and hardware acceleration

CMAX-CAMEL contributions

CMAX-CAMEL: A Coarse-to-Fine Adaptive, Memory-Efficient, and Low-Power Edge Processor for Contrast Maximization Kyeongpil Min, Jongin Choi, Kyeongwon Lee, and Woojoo Lee arXiv :2605 .24017v2 [ cs .AR] 11 Jul 2026 Abstract Contrast maximization (CMAX) is a direct geometric framework for event-based motion estimation, but its iterative warp-and-accumulate pipeline incurs input-dependent computation and frequent memory accesses, challenging real-time, low-power edge deployment. We present CMAX-CAMEL, a coarse-to-fine adaptive, memoryefficient, low-power edge processor for CMAX. CMAX-CAMEL combines a runtime-adaptive execution strategy with a memorycentric processor architecture. It adjusts coarse-to-fine execution according to the observed event distribution, prioritizing stages likely to improve estimation accuracy while suppressing low-value iterations and unnecessary stage transitions. Architecturally, a banked parallel memory organization sustains real-time throughput while reducing latency, and a subsampling-coupled accumulation structure lowers memory-access activity along the warp-andaccumulate dataflow. On a Virtex FPGA prototype operating at 200 MHz, CMAX-CAMEL improves estimation accuracy by up to 19% over fixed coarse-to-fine schedules, reduces processing latency by 53.3%, lowers effective memory accesses by 42%, and cuts total system energy by 52.2%, including adaptation overheads. These results show that CMAX-CAMEL is an HW–SW co-design that co-optimizes execution policy and data movement for real-time, low-power event-based motion estimation at the edge. 1 Introduction Autonomous and mobile edge systems require motion estimation that remains reliable under fast motion, abrupt illumination changes, and stringent energy and latency constraints [1, 2] This capability is a fundamental front-end component of visual SLAM and odometry, where the ego-motion of a camera must be inferred from sequential observations [3, 4] . Event cameras, especially Dynamic Vision Sensors (DVS) [5], are well suited to this setting because they asynchronously report local brightness changes [6–8] . They offer microsecond-level temporal resolution and wide dynamic range for handling fast motion and challenging lighting, while generating sparse outputs that reduce data movement [9, 10] . Under the resource and power constraints of edge deployment, however, pure event-based pipelines remain particularly attractive because they operate directly on the event stream without relying on auxiliary sensing modalities or power-hungry inference [11–13] . Within this This paper has been accepted for publication in the Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2026 . This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by MSIT (No. RS-2024-00345668), and in part by Institute of Information & communications Technology Planning & Evaluation (IITP) grants funded by MSIT (No. RS-2023-00277060) . Kyeongpil Min and Jongin Choi contributed equally to this work. Woojoo Lee is the corresponding author. ISLPED’26, Evanston, Illinois, USA 2026. class of methods, contrast maximization (CMAX) [14], which estimates motion by warping events to maximize the contrast of an accumulated event image, has emerged as a representative geometric framework and has been extended to rotational motion estimation, SLAM, and motion segmentation [15–21] . Yet, despite substantial algorithmic progress, processor-and system-level support needed to make CMAX a practical real-time, low-power primitive for edge platforms remains limited. Recent efforts have explored both coarse-to-fine execution and hardware acceleration for CMAX [22, 23] . Collectively, these studies suggest two key design opportunities: the utility of CMAX computation is highly non-uniform across stages and iterations, and the repeated warp-and-accumulate dataflow can benefit substantially from dedic

FAQs

What problem does CMAX-CAMEL target in contrast maximization pipelines?

CMAX-CAMEL targets input-dependent computation and frequent memory accesses in the iterative warp-and-accumulate process, which hinder real-time, low-power execution on edge devices.

How does CMAX-CAMEL adapt coarse-to-fine execution?

It dynamically adjusts execution stages according to the observed event distribution, prioritizing stages likely to improve estimation accuracy while suppressing low-value iterations and unnecessary transitions.

What architectural techniques reduce latency and memory-access activity?

CMAX-CAMEL uses a banked parallel memory organization for sustained real-time throughput and a subsampling-coupled accumulation structure to lower memory-access activity along the warp-and-accumulate dataflow.

Jul 16, 2026

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