Accurate Machine-Learning-Based On-Chip Router Modeling - Abstract and Key Results

Sep 16, 2026

Uploaded by Mason

As multicore chips become widespread, networks-on-chip (NoCs) serve as the scalable interconnect fabric, making early estimates of power, performance, and area critical under tight power constraints. The work presents accurate architecture-level on-chip router cost models built with machine-learning-based regression. Benchmarked against established approaches such as ORION 2.0 and parametric models, the proposed models reduce estimation error by up to 89% on average. The study targets improved design exploration accuracy and better power-delay-area tradeoff decisions.

LanguageEnglish

CategoryPresentations

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Pages5

Reading Time2 min

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Abstract

Index Terms

Introduction

Networks-on-Chips and Motivation

Limitations of Template-Based Estimation

Proposed Machine-Learning Modeling Paradigm

Contributions

Accurate Machine-Learning-Based On-Chip Router Modeling Kwangok Jeong, Student Member, IEEE, Andrew B. Kahng, Fellow, IEEE, Bill Lin, Senior Member, IEEE, and Kambiz Samadi, Student Member, IEEE Abstract—As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the ﬁrst-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average. Index Terms—Machine learning, nonparemetric regression, on-chip networks. I. INTRODUCTION N ETWORKS-ON-CHIPS (NoCs) are emerging as the de facto interconnection fabric of choice for both general-purpose chip multiprocessors (CMPs) [10], [15] and application-speciﬁc multiprocessor systems-on-chip (MPSoCs) [5],[13]. With increasing core counts, there is a corresponding increase in communication demands in multicore designs to facilitate high core utilization and the corresponding critical need for high-performance NoCs. With many opposing parameters, effective early-stage design exploration is essential to enable the realization of achievable power-delay-area tradeoffs. Existing architectural estimation methods in the literature can be broadly classiﬁed as template-based approaches: in one way or another, these existing methods assume a speciﬁc architecture and underlying circuit implementation in their modeling efforts. The template-based estimation approach is exempliﬁed by the widely-used early-stage NoC power estimation tool ORION [16], and its enhanced successor ORION 2 .0 [8] . The template-based approach has two fundamental limitations. First, for the power and area estimations to be accurate, the actual router microarchitecture used for implementation must closely match the microarchitecture assumed. The second limitation of template-based estimation is the difﬁculty of Manuscript received March 09, 2010; accepted April 16, 2010 . Date of publication May 27, 2010; date of current version September 17, 2010 . This letter draws on preliminary accounts published at ISOCC-09 [7] andASPDAC-10 [9] . This manuscript was recommended for publication by S. K. Shukla. K. Jeong, B. Lin, and K. Samadi are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0409 USA (e-mail: [kjeong@vlsicad.ucsd.edu](kjeong@vlsicad.ucsd.edu), [billlin@ece.ucsd.edu](billlin@ece.ucsd.edu); [ksamadi@ucsd.edu](ksamadi@ucsd.edu)) . A. B. Kahng is with the Department of Computer Science and Engineering, and the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0404 USA (e-mail: [abk@ucsd.edu](abk@ucsd.edu)). Color versions of one or more of the ﬁgures in this letter are available online at [http://ieeexplore.ieee.org](http://ieeexplore.ieee.org). Digital Object Identiﬁer 10.1109/LES.2010.2051413 capturing effects of different application-speciﬁc integrated circuit (ASIC) implementation ﬂows and ﬂow options. Other template-based approaches are based on parametric models [1], [2], [4], [12] . These approaches also assume aspeciﬁc underlying router microarchitecture, requiring the development of new models for different microarchitectures. For parametric models the modeler needs full comprehension of the underlying router microarchitecture in order to come up with a relevant parametric model. Moreover, it is difﬁcult to capture conﬁguration parameter interactions that may gain signiﬁcance as the design complexity increases. Finally, most existing parametric modeling approaches fail to consider implementation ﬂow parameters in their models. To quantify the above limitations

FAQs

Why is early estimation of NoC power, performance, and area important?

Power becomes a first-order design constraint in multicore chips, so early-stage estimates are crucial for effective design exploration and power-delay-area tradeoff decisions.

What is the main limitation of template-based NoC router modeling approaches?

They require the implemented router microarchitecture to closely match the assumed architecture, and they struggle to capture effects of different implementation flows and configuration interactions.

How do the proposed machine-learning router models perform compared with existing models?

The models reduce estimation error by up to 89% on average when compared with ORION 2.0 and parametric models.

Sep 16, 2026

Uploaded by Mason