Unit 2 - Circuit Design Process - NMOS/CMOS Stick Diagrams & Design Rules

Oct 29, 2026

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Unit 2 explains the circuit design process for MOS technologies with an emphasis on converting schematics into stick diagrams and mask/layout representations. It details the four basic fabrication layers and how insulating oxide separates them, then presents color/encoding conventions for NMOS, CMOS, and related structures. The chapter compares n- and p-transistor representation in CMOS style, discusses inverter and NAND/NOR stick-diagram construction, and covers dynamic shift-register layout concepts. It concludes with scalable λ-based design rules, including width, spacing, and gate overhang, and introduces vias as metal interconnects.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages11

Reading Time28 min

AccessFree to download

Circuit Design Process

MOS Layers and Oxide Isolation

Stick Diagrams and Encodings (NMOS)

CMOS Encodings and Transistor Representation

nMOS Inverter, NAND/NOR, and Logic Functions

NMOS vs CMOS Design Style

Design Rules (Width, Spacing, Gate Overhang)

What is Via?

Unit 2 Circuit Design Process In this chapter we will be studying how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: 􀀁 N-diffusion 􀀁 P-diffusion 􀀁 Polysilicon 􀀁 Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. Stick diagrams: Stick diagrams may be used to convey layer information through the use of a color code. For example: n-diffusion--green Encodings for NMOS poly blue yellow black process: --red --metal --implant --contact areas Figure 1: NMOS encodings Figure shows the way of representing different layers in stick diagram notation and mask layout using nmos style. Figure1 shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion mode transistor is represented in the stick format. Encodings for CMOS process: Figure 2: CMOS encodings Figure 2 shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure 2 also shows when a p-transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely. Encoding for BJT and MOSFETs: Figure 3: Bi CMOS encodings There are several layers in an nMOS chip: _ a p-type substrate _ paths of n-type diffusion _ a thin layer of silicon dioxide _ paths of polycrystalline silicon _ a thick layer of silicon dioxide _ paths of metal (usually aluminium) _ a further thick layer of silicon dioxide with contact cuts through the silicon dioxide where connections are required. The three layers carrying paths can be considered as independent conductors that only interact where polysilicon crosses diffusion to form a transistor. These tracks can be drawn as stick diagrams with _ diffusion in green _ polysilicon in red _ metal in blue using black to indicate contacts between layers and yellow to mark regions of implant in the channels of depletion mode transistors. With CMOS there are two types of diffusion: n-type is drawn in green and p-type in brown. These are on the same layers in the chip and must not meet. In fact, the method of fabrication required that they be kept relatively far apart. Modern CMOS processes usually support more than one layer of metal. Two are common and three or more are often available. Actually, these conventions for colors are not universal; in particular, industrial (rather than academic) systems tend to use red for diffusion and green for polysilicon. Moreover, a shortage of colored pens normally means that both types of diffusion in CMOS are colored green and the polarity indicated by drawing a circle round p-type transistors or simply inferred from the context. Colorings for multiple layers of metal are even less standard. There are three ways that an nMOS inverter might be drawn: Figure 4: nMOS depletion load inverter Figure4 shows schematic, stick diagram and corresponding layout of nMOS depletion load inverter Figure 5: CMOS inverter Figure 5 shows the schematic, stick diagram and corresponding layout of CMOS inverter Figure 6: nMOS depletion load NAND and NOR stick diagram Figure6 shows the stick diagrams for nMOS NOR and NAND. Figure 7: stick diagram of a given function f. Figure 7 shows the stick diagram nMOS implementation of the function f=[(xy)+z]’ Figure 8: stick diagram of CMOS NAND and NOR Figure 8 shows the stick diagram CMOS NOR and NAND, where we can see that the p diffusion line never touched the n diffusion directly, it is always joined using a blue color metal line. NMOS and CMOS Design style: In the NMOS style of representing the sticks for the circuit, we use only NMOS transistor, in CMOS we need to differentiate n and p transist

FAQs

What are the four basic layers used to form MOS circuits, and how are they separated?

MOS circuits are formed on N-diffusion, P-diffusion, polysilicon, and metal layers. These layers are isolated from each other by thick or thin silicon dioxide insulating layers.

How are stick diagrams used to represent layer information for NMOS and CMOS?

Stick diagrams convey layer information through encoding, such as using green for n-diffusion and red for poly. For CMOS, n-type and p-type diffusion are drawn in different colors (commonly green and brown), and transistor types are separated by a demarcation line in monochrome style.

What design-rule parameter λ means in scalable Mead–Conway rules?

Mead and Conway provide simplified scalable λ-based rules where the minimum feature size is characterized as 2λ. Width and spacing requirements are expressed in λ and then converted to actual dimensions based on the chosen technology scale.

Oct 29, 2026

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