SLTA055 - Input and Output Capacitor Selection - February 2006 Application Report

Oct 12, 2026

Application Report SLTA055–February 2006 explains how switching-regulator design requirements govern the selection of input and output capacitors. It details key electrical concerns such as ripple-voltage reduction at the regulator input, transient load behavior, allowable voltage deviation, and capacitor impedance limits. Guidance covers minimizing PCB area and capacitor cost, selecting low-ESR ceramic capacitors close to regulator pins, and calculating minimum ceramic capacitance from load current, duty cycle, switching frequency, efficiency, and maximum peak-to-peak ripple voltage.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages11

Reading Time28 min

AccessFree to download

Contents

1 Input Capacitor Selection

2 Output Capacitor Selection

Application Report SLTA055–FEBRUARY 2006 Input and Output Capacitor Selection Jason Arrigo PMP Plug-In Power ABSTRACT When designing with switching regulators, application requirements determine how much input an output capacitance is needed. There are a number of key concerns which effect your selection. The electrical performance requirements of your design play a big part in determining the amount of capacitance required. The transient requirements of your system are very important. The load transient amplitude, voltage deviation requirements, and capacitor impedance each affects capacitor selection. Other important issues to consider are minimizing PCB area and capacitor cost. When selecting input and output capacitance each design has specific requirements which much be addressed. System requirements set hard limits for a design. Depending on what you are trying to accomplish, the amount and type of capacitance can vary. Contents 1 Input Capacitor Selection .......................................................................... 2 2 Output Capacitor Selection ........................................................................ 7 List of Figures 1 Input Pulse Current vs Duty Cycle ............................................................... 2 2 Input Ripple Voltage Plots ......................................................................... 4 3 Multiple POL Modules Example .................................................................. 6 4 Capacitor Impedance Characteristics ............................................................ 7 5 Impedance Limits ................................................................................... 8 6 Regulator Slew Rate Example Circuit ........................................................... 9 7 High Frequency Impedance Plot ................................................................ 10 SLTA055–FEBRUARY 2006 Input and Output Capacitor Selection 1 Submit Documentation Feedback 1 Input Capacitor Selection 1. 1 Reduce Input Ripple Voltage The first objective in selecting input capacitors is to reduce the ripple voltage amplitude seen at the input of the module. This reduces the rms ripple current to a level which can be handled by bulk capacitors. Ceramic capacitors placed right at the input of the regulator reduce ripple voltage amplitude. Only ceramics have the extremely low ESR that is needed to reduce the ripple voltage amplitude. These capacitors must be placed close to the regulator input pins to be effective. Even a few nanohenries of stray inductance in the capacitor current path raises the impedance at the switching frequency to levels that negate their effectiveness. Large bulk capacitors do not reduce ripple voltage. The ESR of aluminum electrolytics and most tantalums are too high to allow for effective ripple reduction. Large input ripple voltage can cause large amounts of ripple current to flow in the bulk capacitors, causing excessive power dissipation in the ESR parasitic. To reduce the rms current in the bulk capacitors the ripple voltage amplitude must be reduced using ceramic capacitors. As a general rule of thumb, keeping the peak to peak ripple amplitude below 75 mV keeps the rms currents in the bulk capacitors within acceptable limits. 1. 2 Selecting Input Ceramic Capacitors Load current, duty cycle, and switching frequency are several factors which determine the magnitude of the input ripple voltage. The input ripple voltage amplitude is directly proportional to the output load current. The maximum input ripple amplitude occurs at maximum output load. Also, the amplitude of the voltage ripple varies with the duty cycle of the converter. For a single phase buck regulator, the duty cycle is approximately the ratio of output to input dc voltage. A single phase buck regulator reaches its maximum ripple at 50% duty cycle. Figure 1 shows the ac rms, dc, and total rms input current vs du

FAQs

Why must ceramic capacitors be placed close to the regulator input pins?

Ceramic capacitors provide the extremely low ESR needed to reduce ripple voltage, but stray inductance in the capacitor current path can raise impedance at the switching frequency and negate their effectiveness.

What determines the input ripple voltage amplitude?

Input ripple voltage amplitude depends on load current, duty cycle, and switching frequency. For a single-phase buck regulator, maximum ripple occurs at about 50% duty cycle and scales with output-to-input voltage ratio.

How is the minimum required ceramic input capacitance calculated?

The report uses an equation that relates the minimum ceramic capacitance to steady-state output load current, duty cycle, switching frequency, maximum allowed peak-to-peak ripple voltage, efficiency, and duty-cycle-related variables.

Oct 12, 2026

Upload by MrHarris58