SLIDE-x-ML - System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations

Aug 6, 2026

Electronic Design Automation (EDA) underpins the development of electronic systems, while High-Level Synthesis (HLS) accelerates hardware design by translating C/C++/SystemC specifications into HDL. For large designs, HLS can remain prohibitively time-consuming. This work introduces an approach and related frameworks to build datasets (SLIDE-x) enabling machine-learning-driven timing and resource estimation (SLIDE-x-ML), including a data-driven feature-creation component that supports multiple input representations and ML methods.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages5

Reading Time13 min

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Abstract

Introduction

High-Level Synthesis and the Need for Faster Estimation

Prior ML-Based EDA and Performance Estimation Tools

Proposed ML-Based Timing and Resource Estimation Approach

Frameworks for Data Extraction and Prediction

VU Research Portal SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations Muttillo, Vittoriano; Stoico, Vincenzo; Santic, Marco; Valente, Giacomo; Pomante, Luigi; Frigioni, Daniele published in 2024 IEEE 42nd International Conference on Computer Design (ICCD) 2024 DOI (link to publisher) 10.1109/ICCD63220.2024.00098 document version Publisher's PDF, also known as Version of record document license Article 25fa Dutch Copyright Act Link to publication in VU Research Portal citation for published version (APA) Muttillo, V. , Stoico, V. , Santic, M. , Valente, G. , Pomante, L. , & Frigioni, D. (2024) . SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations. In 2024 IEEE 42nd International Conference on Computer Design (ICCD): [Proceedings](pp. 616-619) .(Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors) . Institute of Electrical and Electronics Engineers Inc.. [https://doi.org/10.1109/ICCD63220.2024.00098](https://doi.org/10.1109/ICCD63220.2024.00098) General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. E-mail address: [vuresearchportal.ub@vu.nl](vuresearchportal.ub@vu.nl) [Download date: 19](Download date: 19) . Mar. 2026 2024 IEEE 42nd International Conference on Computer Design (ICCD) ©2024 IEEE DOI: 10.1109/ICCD63220.2024.00098| 979-8-3503-8040-8/24/$31.00 | 2024 IEEE 42nd International Conference on Computer Design (ICCD) SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations Vittoriano Muttillo University of Teramo Teramo, Italy vmuttillo@unite.it Vincenzo Stoico Vrije Universiteit Amsterdam Amsterdam, The Netherlands [v.stoico@vu.nl](v.stoico@vu.nl) Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni University of L’Aquila L’Aquila, Italy {marco.santic,giacomo.valente,luigi.pomante,[daniele.frigioni](daniele.frigioni}@univaq.it)[}](daniele.frigioni}@univaq.it)[@univaq.it](daniele.frigioni}@univaq.it) Abstract—Electronic Design Automation (EDA) is a crucial research area related to the development of electronic systems. In particular, High-Level Synthesis (HLS) simplifies HW design by automatically translating C/C++/SystemC specifications into HW description languages. However, HLS for large systems can be time-consuming. In recent years, Machine Learning (ML) has emerged as a prominent topic in EDA, with numerous studies demonstrating its potential to enhance EDA methods covering nearly all phases of the HW design flow. In such a context, this work presents an approach and related frameworks to collect datasets (i.e., SLIDE-x) useful for performing HLS timing and resource estimation through ML techniques (i.e., SLIDE-x-ML), introducing a data-driven component for feature creation that enhances predictions through various input representations and ML methods. Index Terms—high-level synthesis; performance prediction; machine learning; embedded system; electronic design automation. I. INTRODUCTION In the last thirty years, as the Electro

FAQs

What problem does SLIDE-x-ML address in High-Level Synthesis workflows?

SLIDE-x-ML targets the long turnaround time of HLS for large systems by enabling machine-learning-based timing and resource estimation. It supports predicting metrics such as clock cycles, maximum achievable frequency, and hardware resource usage.

How are datasets created for the machine-learning models?

The approach uses SLIDE-x to extract extensive data from C (micro-)benchmarks, combining code execution data, static analysis, and information from HLS reports. This dataset supports training and improves predictions.

What frameworks and components are part of the proposed solution?

Two frameworks are presented: SLIDE-x for dataset extraction and SLIDE-x-ML for training ML models and producing predictions. A data-driven feature-creation component is included to enhance prediction quality using different input representations and ML methods.

Aug 6, 2026

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