Silicon Photonic 2.5D Interposer Networks - for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators

Aug 4, 2026

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Modern machine learning workloads demand ever-higher memory capacity, communication bandwidth, and computation, making monolithic single-chip accelerator designs unable to meet energy-efficiency and throughput requirements. Although 2.5D chiplet accelerators improve scalability by using interposers for high-bandwidth links, metallic interconnects introduce energy, latency, and bandwidth scaling limits. This paper proposes leveraging silicon photonics to enable energy-efficient, high-throughput 2.5D interposer network architectures for scale-out ML hardware accelerators.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages4

Reading Time10 min

AccessFree to download

Introduction

Motivation and limitations of metallic interconnects

Role of silicon photonics and communication patterns

Related Work

Prior SiPh interposer networks for ML workloads

Cross-layer optical CNN and extensions

Overview of Silicon Photonics

Core device concepts and capabilities

Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators Febin Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha Department of Electrical and Computer Engineering Colorado State University Fort Collins, Colorado, USA {febin.sunny, ebad.taheri, mahdi.nikdast, [sudeep}@colostate.edu](sudeep}@colostate.edu) Abstract—Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energyefficient and high throughput 2.5D ML accelerator architectures. Keywords—2.5D chiplet platforms, machine learning, silicon photonics, interposer networks, manycore computing I. INTRODUCTION As modern machine learning (ML) applications scale in terms of memory use, communication bandwidth, and computational requirements at an unprecedented rate, systemlevel solutions to address these requirements are becoming a necessity. Larger ML hardware accelerator chips capable of higher computational throughput are emerging to meet these needs [1]. However, incorporating such computing capacity on a monolithic, single-chip architecture is difficult [2]. The challenges range from power and thermal restrictions to low fabrication yield [3]. As a result, modern accelerator architectures are moving towards 2.5D architectures, where multiple smaller chiplets are connected over an interposer, enabling high bandwidth communication and high throughput ML acceleration through co-packaging memory and processing. 2.5D integration has already found success in commercial accelerators and GPUs [4]. However, with emerging ML models such as transformers (used in large language models (LLMs)) becoming increasingly complex, these 2.5D platforms need to support very high bandwidths between chiplets. While state-ofthe-art electrical wires on interposers can offer bandwidths approaching hundreds of Gb/s with an energy-efficiency of a few pJ/bit [5], there is a need to scale beyond 10 Tb/s bandwidth and fJ/bit energy efficiency, to sustain ML-related data transfer demands between chiplets. However, attenuation and intersymbol interference from dispersion become significant issues at higher frequencies in electrical wires, limiting cutoff rates to 40 Gb/s [6]. Thus, electrical wires cannot meet the data transfer needs of emerging chiplet platforms for ML acceleration. Silicon photonic (SiPh) interconnects can overcome the high energy consumption, limited bandwidth, and high latency of metallic interconnects [7]. SiPh links have many advantages in 2.5D platforms, including minimal signal attenuation, high bandwidth, low energy consumption, and the ability to leverage the mature CMOS ecosystem for low-cost fabrication. Further, ML workloads exhibit broadcast and multicast communication patterns [8] which can be efficiently implementable using networks of SiPh links [9]. Photonic devices can also be used to perform energy-efficient and high throughput ML computational operations, e.g., matrix multiplications [10]. In this paper, we highlight two innovations to enable scaleout hardware acceleration of ML workloads that benefit from SiPh in 2.5D chiplet platforms. The first contribution, TRINE (first discussed in [11]), is a novel 2.5D SiPh interposer network designed to efficiently connect electronic chiplets executing ML workloads. The second contribution, 2.5D-CrossLight (first discussed in [12]) extends the scope by utilizing SiPh for both communication and computation in 2.5D chiplet platforms. II. RELATED

FAQs

Why do metallic interconnects limit 2.5D scale-out ML accelerator performance?

At higher signaling frequencies, attenuation and intersymbol interference from dispersion become significant, restricting achievable cutoff rates to around tens of Gb/s and preventing electrical wires from meeting emerging bandwidth and energy targets between chiplets.

How does silicon photonics improve communication for 2.5D interposer networks?

Silicon photonic links offer minimal signal attenuation, high bandwidth, and low energy consumption compared with metallic interconnects, and they fit ML traffic patterns such as broadcast and multicast via optical network implementations.

What two innovations does the paper propose for scale-out ML acceleration in 2.5D chiplet platforms?

It introduces TRINE, a novel 2.5D silicon photonic interposer network connecting electronic chiplets for ML workloads, and 2.5D-CrossLight, which extends silicon photonics to support both communication and computation for scale-out ML inference on 2.5D platforms.

Aug 4, 2026

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