ScratNet Swin-Based Multi-Scale Dilated Network with Precision Refinement for Semiconductor Scratch Segmentation

Jul 16, 2026

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Surface scratch defects in semiconductor manufacturing create major inspection difficulties due to irregular geometry, low contrast, and varying defect scales across imaging conditions. Existing methods—especially CNN-based approaches—may miss fine edge details needed for reliable pixel-level segmentation. ScratNet introduces an end-to-end segmentation framework using a modified Swin Transformer encoder plus a tailored decoder. The decoder combines MDA for multi-scale context, SIM for spatial detail restoration, and a Precision Refinement branch with anisotropic convolutions to sharpen boundaries and improve thin, irregular defect detection.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages13

Reading Time33 min

Introduction

Challenges in semiconductor scratch inspection

Limitations of traditional inspection methods

Advances in deep learning and transformer-based segmentation

Research objective and pixel-level defect requirements

ScratNet: A Swin-Based Multi-Scale Dilated Network with Precision Refinement for Semiconductor Scratch Segmentation Sachin Ranjan and Hoon Kim arXiv :2607 . 10214v1 [ cs .CV] 11 Jul 2026 Abstract—Surface scratch defects in semiconductor manufacturing pose significant challenges due to their irregular shapes, low contrast, and varying scales. Traditional inspection methods often struggle to detect such defects reliably, especially in complex imaging scenarios. While deep learning approaches based on Convolutional Neural Networks (CNNs) have improved accuracy, they often fail to capture fine-grained edge details. To address these limitations, we propose ScratNet, a novel end-toend scratch segmentation framework that integrates a modified Swin Transformer backbone with a tailored decoder. The decoder incorporates a Multi-Scale Dilated Aggregation (MDA) module to capture both local and global context, a Stem Integration Module (SIM) to restore spatial detail, and a Precision Refinement (PR) branch that enhances boundary sharpness using anisotropic convolutions. Through this stage-adaptive feature aggregation and boundary-aware refinement, ScratNet achieves superior accuracy on thin and irregular defects. Extensive experiments demonstrate that ScratNet consistently outperforms existing methods, providing a scalable and robust solution for automated scratch inspection in high-precision manufacturing. Index Terms—scratch segmentation, silicon wafer, vision transformer, semiconductor I. INTRODUCTION Silicon chips are fundamental to modern technologies including the internet-of-things (IoT), telecommunications, automotive systems, and artificial intelligence (AI) and are a key driver of industrial growth. Semiconductor manufacturing involves hundreds of intricate steps, with defects potentially arising at any stage. Surface defects, particularly scratches, can significantly degrade device performance and reliability, resulting in lower yields and increased production costs [1] . As demand for integrated circuits (ICs) continues to grow, faster and more complex production processes have further increased the risk of manufacturing defects. These defects can originate from various sources such as robotic handling, contamination, leaks, or process variations, making effective defect detection and segmentation essential for maintaining high productivity and quality control. Given the direct impact of IC substrate quality on the performance of final semiconductor products, rigorous inspection remains a critical step in the manufacturing process. However, maintaining consistent wafer quality throughout production S. Ranjan is with the Machine Intelligence and Data Science (MINDS) Lab and the M.S. Program in Electronics Engineering, Incheon National University, Incheon 22012, South Korea. H. Kim is with the Machine Intelligence and Data Science (MINDS) Laband the Department of Electronics Engineering, Incheon National University, Incheon 22012, South Korea) . is a complex and ongoing challenge. Surface scratches, in particular, are among the most common and critical defects, yet they remain difficult to detect reliably using conventional techniques. Traditional inspection methods, such as manual visual inspection and rule-based image processing typically rely on handcrafted features and operator expertise [2] . These approaches are labor-intensive, slow, and prone to inconsistency [3]–[5], especially as device geometries shrink and integration density increases [6] . Furthermore, they often lack a reliable defect-free reference image, limiting their ability to accurately distinguish true defects from process variations. To address these limitations, the semiconductor industry is increasingly turning to automated and intelligent inspection technologies. These methods aim to improve detection accuracy, reduce material waste, and support higher yields by effectively identifying defects at various stages of production [7]–[9] .

FAQs

What makes semiconductor scratch segmentation difficult in practice?

Scratches are irregular, low-contrast, and vary in scale, while industrial images also suffer from noise, illumination variation, and complex surfaces. These factors complicate both detection and accurate pixel-level segmentation.

How does ScratNet improve over typical CNN-based approaches?

ScratNet uses a modified Swin Transformer backbone to better model local and global context and includes a decoder designed to restore spatial detail. It further refines boundaries with a Precision Refinement branch using anisotropic convolutions to capture fine edge information.

What role do the decoder components (MDA, SIM, PR) play in ScratNet?

MDA aggregates multi-scale local and global features, SIM restores spatial detail, and PR enhances boundary sharpness for precise segmentation. Together, they support stage-adaptive feature aggregation and boundary-aware refinement.

Jul 16, 2026

Upload by Ezra