Multiscale simulation and machine learning facilitated design of two-dimensional nanomaterials-based tunnel field-effect transistors: A review - review

Aug 6, 2026

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Traditional complementary metal–oxide–semiconductor (CMOS) and metal–oxide–semiconductor field-effect transistors face scaling limits of Moore’s law, including higher leakage currents, stronger short-channel effects, and quantum tunneling through the gate oxide that degrades ideal device behavior. Tunnel field-effect transistors (TFETs) switch using band-to-band tunneling, enabling subthreshold swing below 60 mV/decade, lower power consumption, and sustained scaling. This review covers TFET design and operation, highlighting optimization via material selection and advanced multi-scale simulation, including machine learning-driven approaches for two-dimensional materials.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages24

Reading Time1 h 0 min

AccessFree to download

Introduction

Motivation from CMOS/MOSFET scaling limits

TFET switching via band-to-band tunneling

Design trade-offs and performance metrics

Role of material systems and heterojunctions

Multi-scale modeling and simulation workflows

APL Machine Learning ARTICLE [pubs.aip.org/aip/aml](pubs.aip.org/aip/aml) Multiscale simulation and machine learning facilitated design of two-dimensional nanomaterials-based tunnel field-effect transistors: A review | Cite as: APL Mach. Learn. 3, 016115 (2025); doi: 10. 1063/5.0240004 Submitted: 4 October 2024 • Accepted: 17 February 2025 •
Published Online: 17 March 2025 | | | | | --- | --- | --- | --- | | Chloe Isabella Tsang,1 Haihui Pu,1 , 2 and Junhong Chen1 , 2, a) | | | | | AFFILIATIONS
1 Pritzker School of Molecular Engineering, University of Chicago, Chicago, Illinois 60637, USA
2 Chemical Sciences and Engineering Division, Physical Sciences and Engineering Directorate, Argonne National Laboratory, Lemont, Illinois 60439, USA
a)Author to whom correspondence should [be addressed:](be addressed: junhongchen@uchicago.edu)[ junhongchen@uchicago.edu](be addressed: junhongchen@uchicago.edu) | | | | | ABSTRACT
Traditional transistors based on complementary metal–oxide–semiconductor and metal–oxide–semiconductor field-effect transistors are facing significant limitations as device scaling reaches the limits of Moore’s law. These limitations include increased leakage currents, pronounced short-channel effects, and quantum tunneling through the gate oxide, leading to higher power consumption and deviations from ideal behavior. Tunnel Field-Effect Transistors (TFETs) can overcome these challenges by utilizing the quantum tunneling of charge carriers to switch between on and off states and achieve a subthreshold swing below 60 mV/decade. This allows for lower power consumption, continued scaling, and improved performance in low-power applications. This review focuses on the design and operation of TFETs, emphasizing the optimization of device performance through material selection and advanced simulation techniques. The discussion will specifically address the use of two-dimensional materials in TFET design and explore simulation methods ranging from multi-scale approaches to machine learning-driven optimization.
© 2025 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license ([https://creativecommons.org/licenses/by/4.0/](https://creativecommons.org/licenses/by/4.0/)). [https://doi.org/10.1063/5.0240004](https://doi.org/10.1063/5.0240004) | | | | I. INTRODUCTION Despite the impressive performance of traditional complementary metal–oxide–semiconductor (CMOS) and metal–oxide– semiconductor field-effect transistors (MOSFETs) in the modern electronics industry, the acceleration of technological advancement is beginning to challenge the limits of Moore’s law.1–3 Consequently, alternative transistor devices1,4–6 are being investigated with the objective of overcoming the performance issues that devices such as MOSFETs and CMOS are prone to present.7 The optimal characteristics of a high-performing device include a small subthreshold swing (SS), low power consumption, minimal leakage current, anda high on/off current ratio.8 In particular, an on/off current ratio of more than 104 is ideal, and being in the range of 103–104 is ideal for Tunnel Field-Effect Transistors (TFETs) . An ideal range for the switching voltage is between 0.1 and 0.5 V. Nevertheless, the intrinsic switching mechanism of conventional semiconductor devices represents a significant limitation.9, 10 The operation of traditional semiconductor devices is based on p–n carrier transport, which restricts the SS of these devices to a value exceeding 60 mV/dec.11 Moreover, this also constrains their capacity to achieve reduced power consumption. By operating on a different switching mechanism, namely band-to-band tunneling (BTBT), TFETs can achieve a subthermal threshold swing of less than 60 mV/dec and gain access to a lower switching power.12–16 Consequently, TFETs have been the subject of considerable research and development as a potential solution to

FAQs

Why do conventional CMOS and MOSFETs struggle as device scaling continues?

They exhibit increased leakage currents, pronounced short-channel effects, and quantum tunneling through the gate oxide, which raises power consumption and causes deviations from ideal behavior.

How do TFETs achieve a subthreshold swing below 60 mV/decade?

TFETs use band-to-band tunneling (BTBT) so switching is driven by quantum tunneling of charge carriers rather than p–n carrier transport.

What design factors strongly influence TFET performance?

Material system choice is critical for tunneling rate and subthreshold swing, with heterojunction source–channel interfaces enabling sharper band profiles and higher tunneling probability.

Aug 6, 2026

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