IWR14xx/16xx/18xx/68xx/64xx Industrial Radar Family - Technical Reference Manual - Revised June 2020

Oct 23, 2026

Technical reference manual for the IWR14xx/16xx/18xx/68xx/64xx Industrial Radar Family, providing structured documentation across preface and device-specific sections. Covers introduction and detailed overviews, memory map organization including system interconnect, master subsystem Cortex-R4F, and EDMA mappings, plus integration topics for processor subsystems and key modules such as clocks, DMA, real-time interrupts, watchdog behavior, GPIO, interrupt management, CAN, serial peripheral interfaces, QSPI, ESM, high-speed interfaces, and handshake RAM. Includes both 14xx and 16xx/18xx variants.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages3551

Reading Time149 h 9 min

AccessFree to download

Preface

14xx

14xx Introduction

14xx Memory Map

14xx Integration

16xx/18xx

16xx Introduction

16xx Memory Map

16xx Integration

IWR14xx/16xx/18xx/68xx/64xx Industrial Radar Family Technical Reference Manual Literature Number: SWRU522E May 2017–Revised June 2020 Contents Preface ..................................................................................................................................... 133 1 14xx ................................................................................................................................ 134 1.1 14xx Introduction .......................................................................................................... 135 1.1.1 14xx Overview.................................................................................................... 135 1.1.2 14xx Description ................................................................................................. 135 1.2 14xx Memory Map ........................................................................................................ 138 1.2.1 System Interconnect............................................................................................. 138 1.2.2 Master Subsystem Cortex-R4F Memory Map................................................................ 139 1.2.3 EDMA Memory Map ............................................................................................. 142 1.3 14xx Integration ........................................................................................................... 143 1.3.1 Cortex-R4F Subsystem ......................................................................................... 143 1.3.2 Clock Comparator ............................................................................................... 144 1.3.3 Direct Memory Access Controller (MSS_DMA) .............................................................. 146 1.3.4 Real Time Interrupt (MSS_RTIA) and RTI With Digital Watchdog Timer (MSS_RTIB) ................ 148 1.3.5 General Purpose I/0 (MSS_GIO) .............................................................................. 148 1.3.6 Vectored Interrupt Manager (MSS_VIM) ..................................................................... 149 1.3.7 Controller Area Network (MSS_DCAN) ....................................................................... 152 1.3.8 Multi-Buffered Serial Peripheral Interface Module (MSS_MIBSPIA) ...................................... 153 1.3.9 Serial Peripheral Interface (MSS_SPIB) ...................................................................... 153 1.3.10 Quad Serial Peripheral Interface (MSS_QSPI) ............................................................. 154 1.3.11 Enhanced Direct Memory Access (EDMA) .................................................................. 154 1.3.12 Error Signaling Module (MSS_ESM) ......................................................................... 157 1.3.13 High-Speed Interface (HSI) .................................................................................... 160 1.3.14 Handshake RAM (HSRAM) ................................................................................... 160 2 16xx/18xx......................................................................................................................... 161 2.1 16xx Introduction .......................................................................................................... 162 2.1.1 16xx Overview.................................................................................................... 162 2.1.2 16xx Description ................................................................................................. 162 2.2 16xx Memory Map ........................................................................................................ 166 2.2.1 System Interconnect............................................................................................. 166 2.2.2 Master Subsystem Cortex-R4F Memory Map................................................

FAQs

What is covered in the manual for the 14xx family?

It includes 14xx introduction, an overview, memory map details (system interconnect, Cortex-R4F master subsystem, and EDMA), and integration topics for multiple hardware modules and interfaces.

Which memory map sections are documented for both 14xx and 16xx/18xx?

Both cover system interconnect, the master subsystem Cortex-R4F memory map, and EDMA memory map; the 16xx/18xx section additionally includes a DSP subsystem memory map.

Which integration modules are addressed under the 14xx and 16xx/18xx chapters?

Integration topics cover processor-related subsystems and functional blocks such as clock comparator, DMA, real-time interrupt with watchdog timer, GPIO, vectored interrupt manager, CAN, SPI/QSPI, and other specialized modules listed in the contents.

Oct 23, 2026

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