IgH EtherCAT Master 1 - Feature Summary - Overview

Oct 3, 2026

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IgH EtherCAT Master 1.6.13 documentation revision 1.6.13 dated September 15, 2026 describes the EtherCAT master stack in a structured way. It covers feature summary, licensing, core architecture modules, master phases, process data, and application interfaces including cyclic operation, VoE handlers, distributed clocks, and examples. It further explains Ethernet device networking, state machine theory and models, mailbox protocol implementations (EoE, CoE, VoE, SoE), userspace command-line and library interfaces, timing aspects, and installation/build steps.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages163

Reading Time6 h 51 min

AccessFree to download

Conventions

The IgH EtherCAT Master 1

Feature Summary

License

Architecture

Master Module

Master Phases

Process Data

Application Interface

Master Configuration

Slave Configuration

Cyclic Operation

VoE Handlers

Concurrent Master Access

Distributed Clocks

Application Interface Header

Userspace Application Example

Ethernet Devices

Network Driver Basics

Native EtherCAT Device Drivers

Generic EtherCAT Device Driver

Providing Ethernet Devices

Redundancy

EtherCAT Device Interface

Patching Native Network Drivers

State Machines

State Machine Theory

The Master’s State Model

The Master State Machine

The Slave Scan State Machine

The Slave Configuration State Machine

The State Change State Machine

The SII State Machine

The PDO State Machines

Mailbox Protocol Implementations

Ethernet over EtherCAT (EoE)

CANopen over EtherCAT (CoE)

Vendor specific over EtherCAT (VoE)

Servo profile over EtherCAT (SoE)

Userspace Interfaces

Command-line Tool

Userspace Library

RTDM Interface

System Integration

Debug Interfaces

Timing Aspects

Application Interface Profiling

Bus Cycle Measuring

Installation

Getting the Software

Building the Software

Building the Interface Documentation

Installing the Software

Automatic Device Node Creation

IgH Master 1.6.13 Documentation Dipl.-Ing. (FH) Florian Pose, [fp@igh. de](fp@igh. de)[ ](fp@igh. de)Ingenieurgemeinschaft Essen, September 15, 2026 Revision 1.6.13 ii 1.6. 13, September 15, 2026 Contents Conventions .................................... x 1 The IgH EtherCAT Master 1 1.1 Feature Summary .............................. 1 1.2 License .................................... 3 2 Architecture 5 2.1 Master Module ............................... 7 2.2 Master Phases ................................ 9 2.3 Process Data ................................ 9 3 Application Interface 13 3.1 Master Con􀀌guration ............................ 13 3.1.1 Slave Con􀀌guration ......................... 13 3.2 Cyclic Operation .............................. 15 3.3 VoE Handlers ................................ 17 3.4 Concurrent Master Access ......................... 17 3.5 Distributed Clocks ............................. 19 3.6 Application Interface Header ........................ 22 3.7 Userspace Application Example ...................... 71 4 Ethernet Devices 79 4.1 Network Driver Basics ........................... 79 4.2 Native EtherCAT Device Drivers ..................... 81 4.3 Generic EtherCAT Device Driver ..................... 84 4.4 Providing Ethernet Devices ........................ 85 4.5 Redundancy ................................. 85 4.6 EtherCAT Device Interface ......................... 85 4.7 Patching Native Network Drivers ..................... 86 5 State Machines 87 5.1 State Machine Theory ........................... 88 5.2 The Master's State Model ......................... 90 5.3 The Master State Machine ......................... 93 5.4 The Slave Scan State Machine ....................... 93 5.5 The Slave Con􀀌guration State Machine .................. 96 5.6 The State Change State Machine ..................... 98 1.6. 13, September 15, 2026 iii 5.7 The SII State Machine ........................... 99 5.8 The PDO State Machines ......................... 100 6 Mailbox Protocol Implementations 105 6.1 Ethernet over EtherCAT (EoE) ...................... 105 6.1.1 EoE Interface Con􀀌guration .................... 108 6.2 CANopen over EtherCAT (CoE) ..................... 109 6.3 Vendor speci􀀌c over EtherCAT (VoE) ................... 111 6.4 Servo Pro􀀌le over EtherCAT (SoE) .................... 111 7 Userspace Interfaces 113 7.1 Command-line Tool ............................. 113 7.1.1 Character Devices .......................... 113 7.1.2 Setting Alias Addresses ....................... 114 7.1.3 Displaying the Bus Con􀀌guration ................. 114 7.1.4 Display CRC Error Counters .................... 115 7.1.5 Output PDO information in C Language ............. 115 7.1.6 Displaying Process Data ...................... 116 7.1.7 Setting a Master's Debug Level .................. 116 7.1.8 Con􀀌gured Domains ........................ 116 7.1.9 SDO Access ............................. 117 7.1.10 EoE Statistics ............................ 119 7.1.11 File-Access over EtherCAT ..................... 119 7.1.12 Creating Topology Graphs ..................... 120 7.1.13 Setting Ethernet-over-EtherCAT IP Parameters ......... 120 7.1.14 Master and Ethernet Devices ................... 121 7.1.15 Sync Managers, PDOs and PDO Entries ............. 121 7.1.16 Register Access ........................... 122 7.1.17 Trigger a Bus Scan ......................... 123 7.1.18 SDO Dictionary ........................... 124 7.1.19 SII Access .............................. 124 7.1.20 Slaves on the Bus .......................... 126 7.1.21 SoE IDN Access ........................... 127 7.1.22 Requesting Application-Layer States ............... 129 7.1.23 Displaying the Master Version ................... 129 7.1.24 Generating Slave Description XML ................ 129 7.2 Userspace Library .............................. 1

FAQs

What does the documentation describe about the IgH EtherCAT Master?

It describes the EtherCAT master documentation for version 1.6.13, including feature summary, architecture, application interfaces, protocol implementations, userspace tools, timing, and installation steps.

Which main components are covered in the architecture section?

The architecture section covers the master module, master phases and transitions, and process data, forming the basis for how the master operates.

How are userspace interfaces provided in this documentation?

Userspace interfaces include a command-line tool, a userspace library, an RTDM interface, system integration components (scripts and systemd integration), and debug interfaces.

Oct 3, 2026

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