IEICE Electronics Express - Vol.20 No.3 - 1.9-ps 8-phase interpolation TDC with capacitance compensation self-calibration

Sep 17, 2026

Uploaded by Jake

Presents a 1.9-ps 8-phase interpolation time-to-digital converter (PI-TDC) architecture that improves resolution and conversion speed using phase interpolation, high-frequency readout, and reset techniques. The prototype is implemented in 65-nm CMOS at 1-V, achieving 1.9-ps resolution at 2.5-GS/s. Simulated DNL is 0.85-LSB and INL is 0.64-LSB. The PI-TDC is used in a high-speed TB-ADC with a high-performance VTC and CCS-CAL, yielding 8-bit at 1.6-GS/s with PVT robustness and 52.1-fJ/conv.-step (Walden FoM).

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages5

Reading Time13 min

AccessFree to download

Introduction

Proposed technique

8-phase phase interpolation TDC

IEICE Electronics Express, Vol.20, No.3, 1–5 LETTER A 1.9-ps 8􀀂 phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration Zhijie Chen 1 , Xiaoyu Zhang 1 , Yongkuo Ma 1 , Xitong Liang 1 , Xinyu Du 1 , and Peiyuan Wan 1, a) Abstract This paper presents a 1.9-ps 8􀀂 phase interpolation time-todigital converter (PI-TDC) . This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2 .5-GS/s. The simulated DNL is 0 . 85-LSB, and INL is 0 .64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL) . The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step. Keywords: time-to-digital converter (TDC), phase interpolation (PI), voltage-to-time converter (VTC), analog-to-digital converter (ADC), capacitance compensation self-calibration (CCS-CAL), process, voltage, and temperature (PVT) robustness Classiﬁcation: Integrated circuits 1. Introduction After decades of unremitting eﬀorts, convincing new evidence shows that Moore’s Law has almost reached its limit. The “time for space” method has attracted more attention in the design of ultra-deep submicron mixed-signal circuits. The time-to-digital converter (TDC) plays the vital role in data conversion. It is usually applied to measure precise time intervals and provides time-domain solutions for frequency generation and data conversion, such as digital phase-locked loops (DPLL) [1, 2, 3] and time-based analog-to-digital converter (TB-ADC) [4, 5, 6, 7] . The delay-line TDC [8, 9, 10, 11, 12] is the most elementary structure with the merit of simple structure and low power. However, the inherent latency limits the resolution, making it challenging to achieve high-resolution TDC. The Vernier TDC [13, 14, 15, 16] adds an extra delay-line and expands the resolution. Based on Vernier TDC, two-dimensional (2-D) Vernier TDC [17, 18, 19], three-dimensional Vernier TDC [20], and Vernier ring TDC [21, 22] are derived. Two-step TDC [23, 24, 25] improves the speed of Vernier TDC by introducing a time ampliﬁer (TA) . However, the gain of the TA is greatly aﬀected by the process, voltage, and temperature (PVT) . The phase interpolation (PI) technique generates extra time signals, gated 1 Faculty of Information Technology, Beijing University of Technology, Chaoyang District, Beijing, 100124, China a) [wanpy@bjut.edu.cn](wanpy@bjut.edu.cn) DOI: 10.1587/elex.20.20220515 Received November 22, 2022 Accepted December 19, 2022 Publicized January 5, 2023 Copyedited February 10, 2023 inverter PI [26, 27, 28] and voltage division PI [28] are popular. The PI was applied to the delay cell [29], but plenty of PI cells lead to a larger area and higher power consumption. The number of interpolators is reduced by the 4􀀂 PI and 2-D quantization techniques [30] . There is also a restriction between speed and resolution in the above research on TDC. This paper proposed a 1.9-ps 8􀀂 PI-TDC under a 1-V power supply at 2.5-GS/s. The speed and resolution have been enhanced in cooperation with the PI, high-frequency readout, and reset techniques. Taking advantage of speed, the proposed 8􀀂 PI-TDC is applied to a high-speed TBADC in combination with a high-performance voltage-totime converter (VTC) and the capacitance compensation self-calibration (CCS-CAL) . The proposed high-speed TBADC under a 1-V power supply achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting an SNDR of 47.4-dBand a Walden FoM of 52.1-fJ/conv.-step. With the selfcalibration technique, the TB-ADC presents a sub-0.5-bit ENOB drop across a temperat

FAQs

What is the main function of the proposed PI-TDC architecture?

It converts time intervals using an 8-phase interpolation approach to enhance both resolution and conversion speed, supported by high-frequency readout and reset techniques.

What circuit and performance targets does the prototype achieve?

The PI-TDC prototype is implemented in 65-nm CMOS with a 1-V supply, achieving 1.9-ps resolution at 2.5-GS/s, with simulated DNL of 0.85-LSB and INL of 0.64-LSB.

How is the PI-TDC used in the TB-ADC, and what benefits are reported?

It is applied to a high-speed TB-ADC combined with a VTC and CCS-CAL, achieving 8-bit at 1.6-GS/s with PVT robustness and a Walden FoM of 52.1-fJ/conv.-step.

Sep 17, 2026

Uploaded by Jake