GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network

Jul 16, 2026

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Three-dimensional (3D) integration increases transistor density and efficiency but makes power delivery networks (PDNs) harder to analyze as design complexity grows. Reliable through-silicon via (TSV) planning is critical because uneven effective resistance distributions can worsen IR drop. A GPU-accelerated framework is proposed for accurate early-stage effective resistance analysis in 3D IC PDNs. The method uses divide-and-conquer partitioning into 2D sub-networks and specialized conductance-matrix reformulation.

LanguageEnglish

CategoryResearch & Report

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Pages7

Reading Time18 min

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Introduction

Background

Formulation of DC analysis for PDN

Effective resistance of PDN

GPU-Accelerated Effective Resistance Analysis for 3D IC Power Delivery Network Jingchao Hu, Cheng Zhuo, Zhou Jin College of Integrated Circuit, Zhejiang University Abstract—Three-dimensional (3D) integration is a critical technique for enhancing transistor density, improving power efficiency, and reducing interconnect delays. However, as current demandsand design complexity increase, power deliver networks (PDNs) are facing growing challenges. Careful planning of through-silicon vias (TSVs) is essential for ensuring reliable PDNs, where effective resistance serves as a vital metric for the reliability. Ill-planned TSVs often cause 3D IC with unevenly distributed effective resistance and consequently severer IR Drop. In this paper, we propose a GPU-accelerated framework on accurate effective resistance analysis for early stage 3D IC PDNs. The proposed framework achieves a speedup of 5 to 6 orders of magnitude compared to the conventional direct solver, while maintaining deviations in both maximum and average relative errors. I. INTRODUCTION semiconductor industry continues to push the bound- off using standard PSN analysis methods [8]–[18] . However, most existing methods were developed for 2D PDNs and do not fully leverage the structural properties of 3D PDNs, potentially resulting in inefficient computations when applied to 3D ICs. Moreover, early-stage PDN design requires the ability to rapidly evaluate various design options [19] . As the number of stacked dies increases, the number of possible effective resistance paths from the IPs/modules on the bottom tier to the bumps on the top tier also increases exponentially, making traditional methods for analyzing effective resistance computationally expensive and slow. At the early design stage, there exist tens to hundreds of thousands of effective resistance paths from bumps, through TSVs, to the current loads (defined at IPs or modules) in 3DICs. Although some approaches have explored parallel acceleration techniques for general PDN analysis, these methods are not optimized for effective resistance calculations, particularly for the unique structure of 3D ICs. To address these challenges, this paper introduces an advanced GPU-accelerated framework tailored for early-stage effective resistance analysis in 3D IC PDNs. The proposed framework enhances the computation of effective resistance across various bump-load configurations by employing a divide-andconquer strategy that partitions the 3D PDN into multiple 2D sub-networks. This decomposition not only enables efficient GPU-accelerated analysis but also significantly reduces computational complexity, thereby enhancing scalability for larger 3D IC designs. The contributions are summarized as follows: • We introduce a divide-and-conquer strategy that decomposes the 3D PDN into multiple 2D sub-problems, which can be analyzed independently and in parallel to improve the scalability. • We reformulate the original PDN system conductance matrix—initially intended for voltage drop analysis—into a specialized formulation optimized for effective resistance computation, thereby reducing the problem size. • The proposed framework is highly compatible with GPU-acceleration platforms, enabling concurrent computation of effective resistance across multiple bump-load pairs, thus further accelerating the analysis process. The experimental results demonstrate that the proposed framework significantly outperforms the prior works in both efficiency and scalability. For large-scale 3D IC designs, our framework was able to compute effective resistances for millions of bump-load pairs in a matter of seconds, a task that would be nearly infeasible using a golden direct solver [17] or a most recently published effective resistance solver [18] . The results also highlight the scalability of the proposed framework, with runtimes that increase linearly with the total number of nodes and bump-load pairs, making it well-suited for

FAQs

Why is effective resistance important in 3D IC power delivery networks?

Effective resistance is used as a reliability metric in PDNs. Poor TSV planning can create uneven effective resistance distribution, which increases IR drop severity.

What is the main idea of the proposed GPU-accelerated framework?

The framework applies a divide-and-conquer strategy that decomposes the 3D PDN into multiple 2D sub-networks, enabling independent parallel GPU-accelerated analysis.

How does the framework improve computation beyond basic GPU acceleration?

It reformulates the original PDN conductance matrix for effective resistance computation, reducing the problem size, and supports concurrent computation across multiple bump-load pairs.

Jul 16, 2026

Upload by Oliver