Full-stack evaluation of Machine Learning inference workloads for RISC-V systems - slideshare

Aug 3, 2026

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Architectural simulators are essential to RISC-V research, enabling workload evaluation without expensive physical prototypes and supporting rapid iteration on architectural ideas through detailed performance metrics. As deep learning spreads widely, benchmarking new architectures with machine learning workloads becomes critical. This study evaluates diverse ML inference workloads on RISC-V using gem5, paired with an open-source MLIR-based compilation toolchain based on MLIR and IREE runtime support. The results also highlight gem5’s current RISC-V simulation limitations and directions for future refinement.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages2

Reading Time5 min

AccessFree to download

Introduction

Simulation platforms for RISC-V performance evaluation

MLIR and IREE compilation/runtime approach

Experimental setup and results

Overall benchmarking flow and simulator configuration

Benchmark list and input specifications

Full-stack evaluation of Machine Learning inference workloads for RISC-V systems Debjyoti Bhattacharjee, Anmol, Tommaso Marinelli, Karan Pathak, Peter Kourzanov imec, Kapeldreef 75, 3001 Leuven, [Belgium.](Belgium. {first}.{last}@imec.be)[ {](Belgium. {first}.{last}@imec.be)[first](Belgium. {first}.{last}@imec.be)[}](Belgium. {first}.{last}@imec.be)[.](Belgium. {first}.{last}@imec.be)[{](Belgium. {first}.{last}@imec.be)[last](Belgium. {first}.{last}@imec.be)[}](Belgium. {first}.{last}@imec.be)[@imec.be](Belgium. {first}.{last}@imec.be) arXiv :2405 . 15380v1 [ cs .AR] 24 May 2024 Abstract—Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve asa dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement. Index Terms—compilation, embedded, ML, performance I. INTRODUCTION The rapid advancement of deep learning (DL) and their pervasive application across various domains have propelled the need for efficient and accurate simulation platforms to evaluate performance and optimize hardware implementations. Functional simulators such as QEMU [1] and Spike [2] can be used for building software and evaluation of correctness for RISC-V based platforms. They typically do not offer the scope for detailed performance evaluation of a workload. gem5 [3], on the other hand, offers the possibility to evaluate representative performance of workloads, based on a modular description of various architectural components. Furthermore, gem5 has timed models of different kinds of CPUs, such as inorder cores, out-of-order cores, etc., which helps in evaluating different hardware architectures relatively fast by changing simulation configuration parameters. A large number of machine learning frameworks have evolved over time, such as PyTorch, Tensorflow, ONNX, Caffe, etc. Even though most of the frameworks are available with a Python frontend, they have their own operator sets along with specific implementations of runtime. From the perspective of hardware developers, this leads to high development and testing overhead, since the runtime has to be ported for the specific hardware. In order to get around this problem, we focus on using MLIR representation of the ML models [4] . MLIR offers a modern open source compiler infrastructure for multi-level intermediate representations and it resides asa sub-project inside LLVM [5] . We use the open-source IREE ( Integration, Representation, and Execution Environment) framework for compilation and runtime support. IREE (a) MLIR based flow | Deep Learning Models | | | --- | --- | | | | | Framework independent MLIR | | | | | | Hardware dependent code | | | | | | Linux OS | | | gem5 simulator for RV64GC | | (b) Simulated system specifications | Attribute | Type/version | | --- | --- | | Core Type | MinorCPU, O3CPU | | Core Freq. | 2 GHz | | L1 Cache | 64KB, 4-way | | L2 Cache | 8MB, 4-way | | DRAM Type | simpleMem | | DRAM Size | 3GB | | DRAM Freq. | 1 GHz | | Ke

FAQs

Why are architectural simulators important for RISC-V research in this study?

They provide a platform to evaluate workloads without costly physical prototypes and support exploration of architectural concepts via measurable performance metrics.

How does the study compile and run machine learning workloads on RISC-V?

It uses an open-source compilation toolchain based on MLIR, together with the IREE framework to compile, optimize, and execute ML models on supported hardware targets.

What tool is used to evaluate performance of the ML inference workloads on RISC-V?

The study uses gem5, an open-source architectural simulator, to benchmark a wide range of deep learning inference workloads.

Aug 3, 2026

Upload by Liam