Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout

Aug 4, 2026

Embedded field programmable gate array (eFPGA) technology enables reconfigurable logic inside an application-specific integrated circuit (ASIC), combining ASIC low power and efficiency with the flexibility of FPGA configuration. A public open-source framework (“FABulous”) was used to design and verify eFPGAs in 130 nm and 28 nm CMOS. The eFPGA’s front-end readout role was evaluated via particle-sensor simulations. A machine-learning classifier for at-source sensor data reduction was synthesized and configured on the eFPGA, demonstrating proof-of-concept reproduction with perfect accuracy, and outlining further development for collider detector readout.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages17

Reading Time43 min

AccessFree to download

Background

Developments in 130nm CMOS

eFPGA Customization

ASIC Digital Architecture

Fabrication

Testing Results

Simple Counter Test

ASIC Power Draw

Motivation for Transitioning from 130nm to 28nm CMOS Technology

Developments in 28nm CMOS

eFPGA Customization

ASIC Digital Architecture

Fabrication

Testing Results

Simple Counter Test

ASIC Power Draw

AXI Stream Loopback in the eFPGA

Application for Machine Learning-based At-Source Processing

Summary

arXiv :2404 . 17701v5 [ cs .AR] 28 Aug 2024 Prepared for submission to JINST Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout J. Gonski, 1 A. Gupta, 1 H. Jia, 1 ,2 H. Kim, 1 L. Rota, 1 L. Ruckman, 1 A. Dragone, 1 and R. Herbst 1 1 SLAC National Accelerator Laboratory, 2575 Sand Hill Road, M/S 96, Menlo Park, CA 94025, USA 2 Stanford University, 450 Jane Stanford Way, Stanford, CA 94305, USA E-mail: [jgonski@slac.stanford.edu](jgonski@slac.stanford.edu) Abstract: Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC) . This approach offers the low power and efficiency of an ASIC along with the ease ofFPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learningbased classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed. Keywords: Reconfigurable Computing; Open Source; FPGA; ASIC; Machine Learning ArXiv ePrint: 2404.17701 | Contents
1 Background
2 Developments in 130nm CMOS
2.1 eFPGA Customization
2.2 ASIC Digital Architecture
2.3 Fabrication
2.4 Testing Results
2.4.1 Simple Counter Test
2.4.2 ASIC Power Draw
3 Motivation for Transitioning from 130nm to 28nm CMOS Technology
4 Developments in 28nm CMOS
4.1 eFPGA Customization
4.2 ASIC Digital Architecture
4.3 Fabrication
4.4 Testing Results
4.4.1 Simple Counter Test
4.4.2 ASIC Power Draw
4.4.3 AXI Stream Loopback in the eFPGA
5 Application for Machine Learning-based At-Source Processing
6 Summary | 1
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14 | | --- | --- | 1 Background Silicon microelectronics technology is a key part of the modern computational paradigm, offering high performance and low power options for data processing tasks. A diversification of microchip designs offers the ability to customize computing solutions to a particular problem. Common options such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) offer trade-offs between performance, power consumption, and flexibility to suit a wide variety of applications. While an FPGA is fully customizable, it draws more power than an ASIC; however, the ASIC requires considerable expertise to design, and is fixed to a certain task once fabricated. Microelectronics remain a rapidly developing field, with advances promising to deliver even denser logic, faster processing, and novel designs. In parallel, artificial intelligence and machine learning (AI/ML) have become essential tools in data science. In light of increasing dataset sizes and expanding computational capacity, ML-based methodology can execute common scientific tasks such as signal-noise classification, regression of key quantities, fast generation of simulation, or anomaly detection, with good efficiency and performance. Leveraging ML in these scenarios requires a high degree of reconfigurability in computing architecture, such that weights and biases of a model, as well as the model itself, can be updated throughout training and over time as the task evolves. In the sciences, many data proces

FAQs

Why consider embedded FPGA (eFPGA) technology for machine learning in collider readout systems?

eFPGA integrates FPGA-like reconfigurable logic into an ASIC design, aiming to achieve FPGA flexibility with ASIC-like power efficiency. This supports updating model parameters over time while meeting low-power and low-latency constraints.

How were the eFPGAs designed and validated in this work?

An open-source framework called “FABulous” was used to design eFPGAs in 130 nm and 28 nm CMOS technology nodes. The prototypes were then fabricated and verified through structured testing.

What proof-of-concept was demonstrated for the machine learning application on the eFPGA?

A machine-learning-based classifier for reducing sensor data at the source was synthesized and configured onto the eFPGA. The expected algorithm result was reproduced on the eFPGA with perfect accuracy as the demonstration.

Aug 4, 2026

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