EM73C044VCG-SPI-NAND-Flash - Rev-1.2 Advance Revision 1.2

Nov 1, 2026

Uploaded by Logic

SPI NAND Flash datasheet for the Etron EM73C044VCG-H device, covering advance revision 1.2. Provides SPI and Hold mode operation guidance, command descriptions, and detailed write, program, erase, power-on/reset, and One-Time Programmable (OTP) functions. Includes hardware write protection, status register handling, bad block management, and absolute maximum ratings. Also documents package outline information and key characteristics, with a revision history from 1.0 through 1.2 and updates such as ECC protection and spare area.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages40

Reading Time1 h 41 min

AccessFree to download

Contents

1 Introduction

2 Device Operation

3 Commands Description

4 Write Operations

5 Feature Operations

6 Read Operations

7 Program Operations

8 Erase Operation-Block Erase (D8H)

9 Power-On Process and Reset Operation

10 One-Time Programmable (OTP) Function

11 Hardware Write Protection (HWP)

12 Status Register

13 Bad Block Management

14 Absolute Maximum Ratings

15 Characteristics

16 Package Outline Information

List of Figures

SPI NAND Flash Datasheet Serial Peripheral Interface (SPI) Model EM73C044VCG-H Advance Revision 1.2 EtronTech SPI NAND Flash SPI NAND Part Numbering Information Etron SPI NAND Flash devices are categorized in the following diagram based on the features and densities EM7 X X XX X XX X – X Special Code H = Pb and Halogen Free Generation Code G = Version Package Type VC = LGA-8 Package Flash Configuration 4 = SLC SPI NAND Bus Width 04 = x4 Density C = 1Gb D = 2Gb E = 4Gb F = 8Gb Supply Voltage 8 = 1.8V 3 = 3.3V Product Family EM7= Etron SPI NAND Flash Etron Technology, Inc. reserves the right to change products or specification without notice. Etron Technology, Inc. 2 EtronTech SPI NAND Flash Revision History | Rev | Date | Comments | | --- | --- | --- | | 1.0 | September 13 , 2023 | Initial release | | 1.1 | January 10, 2024 | 1. Removed Permanent Block Protection (PBP)
2. Updated DC/AC Characteristics
3. Added HOLD\# Timing | | 1.2 | June 6, 2024 | 1. Added the Table 1-4 ECC Protection and Spare Area | Etron Technology, Inc. 3 EtronTech SPI NAND Flash Contents 1 Introduction.............................................................................................................................7 1.1 Features ............................................................................................................................................... 7 1.2 General Description ............................................................................................................................. 8 1.3 Memory Mapping Diagram .................................................................................................................. 9 1.4 Pin Configuration ............................................................................................................................... 10 1.5 Array Organization ............................................................................................................................. 11 2 Device Operation ..................................................................................................................13 2.1 SPI Mode ........................................................................................................................................... 13 2.2 Hold Mode.......................................................................................................................................... 15 3 Commands Description........................................................................................................16 4 Write Operations...................................................................................................................17 5 Feature Operations...............................................................................................................18 6 Read Operations ...................................................................................................................19 6.1 Read ID (9FH) .................................................................................................................................... 19 6.2 Page Read ......................................................................................................................................... 20 7 Program Operations .............................................................................................................24 7.1 Program Load (PL) (02H) .................................................................................................................. 24 7.2 Program Load x4 IO (PL x4) (32H) .................................................................................................... 25 7.3 Program Execute (PE) (10H) ............................................................................................................. 26 8 Erase Operation-Block Erase (D8H) ........

FAQs

What does the datasheet revision history include for Rev 1.2?

Rev 1.2 (June 6, 2024) adds Table 1-4 ECC protection and spare area. Earlier revisions include removing Permanent Block Protection (PBP) and updating DC/AC characteristics plus adding HOLD# timing.

Which operation modes are described for SPI NAND Flash device operation?

The document describes SPI mode and Hold mode, including how the device operates under each mode.

What are the main functional sections for reading, programming, and erasing?

Reading includes Read ID and page read; programming includes program load and program execute; erasing is covered by block erase (D8H). Power-on process and reset operation are also included.

Nov 1, 2026

Uploaded by Logic