Double-sided probing system for 150µm pitch co-packaged optics - Article overview - probing system design requirements and testing challenges

Nov 2, 2026

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Double-sided probing system requirements are presented for 150µm-pitch co-packaged optics (CPO), driven by heterogeneous integration and silicon photonics trends toward higher-performance Ethernet up to 800G. The article outlines why optical co-packaging improves signal-to-noise versus electrical traces, while manufacturing complexity makes assured yield critical. It specifies probing four top micro-bump sites and bottom LGA pads, then details challenges including fine pitch alignment, 112Gbps speed testing, wide temperature operation (RT to 105ºC), and managing 600W device power with thermal expansion control.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages5

Reading Time13 min

AccessFree to download

Double-sided probing system overview

Background: heterogeneous integration and CPO

Why silicon photonics and co-packaging matter

Test requirements and key challenges

Proposed test module concept

Double-sided probing system for 150µm pitch co-packaged optics By Collins Sun [WinWay Technology] T he focus of the double-sided probing system described in this article is t o be in alignment with trends in networking development . As expected, advanced packaging technology will continue to extend Moore’s Law, particularly the rapid development of heterogeneous integration (HI) . According to various organizations, such as IEEE, SEMI, and ASME, the essential spirit of HI is to integrate different process nodes and application-specific integrated circuit s ( ICs) into a single highend package, such as a 3D structure system-in-package (3D SiP) . When HI is combined with silicon photonics (Si Ph) , trace loss from plug gable optics is greatly reduced and is able to drive higher performance Ethernet applications to 800G (see Figure 1) . Individual active and passive optical components in a package can provide the best performance and cost benefits in a comprehensive manner. However, more sophisticated processes in package assembly also mean that it is critical to have the assured yield after assembling all the discrete chips . Co-packaged optics (C PO) is one representative application—its optical signal has a better signal-to-noise ratio than electrical signals because of the light being transmitted through an optic fiber rather than electrical signals through a copper trace. Having optical engines near the electrical switch to reduce signal trace length in the substrate by advanced package technology is a breakthrough technology. According to Yole Intelligence, the compound annual growth rate (CAGR) of the CPO market is predicted at around 55%, from US$6 million in 2020 to US$2 .2 billion by 2032 [1] . SiPh have been considered a unique t e ch nology for developing highp er for m an c e net worki n g sy st em because of several factors. First, it can be designed and manufactured using current complementary metal-oxide semiconductor (CMOS) processes and equipment, thereby achieving lower cost and higher performance devices . Second, it can be combined with logic and digital circuits for data processing. Third , Si Ph can be designed using different wafer materials, such as III-V compound semiconductors . The future of SiPh will flow into two main streams: co-packaging and chip integration. Copackaging is the 2.5D integration of the CMOS logic or digital chip with optical Figure 1: Development trends in pluggable optics and CPO. SOURCE: Yole Group Chip Scale Review November • December • 2022 [[ChipScaleReview.com](ChipScaleReview.com)] 1 chips connected by the copper trace of substrate . Chip integration is a single complete chip solution that includes different functional ICs using throughsilicon via s (TSVs) both for A SICsand optical die . SiPh are expected to integrate all optical components, such as filter, polarization diversity, and splitter/combine r into a single die, including an active laser, modulator, and photodetector. With the help of SiPh and photonic integrated circuits (PICs), CPO applications will be more competitive overall when compared to conventional pluggable optical modules. The packaged optical component usually requires a smaller form factor with a fine pitch. Therefore, the testing system needs precision alignment for probing C4 sides approximately 150µm from the top side, and it also must overcome thermal expansion when testing at different temperature points. These are the initial requirements for the double-sided probing system for 150µm-pitch CPO. Double-sided probing system Th e t arget e d sp e ci fic at ion s of CPO packaging are listed in Figure 2 . A double-sided probing system is needed to probe four sites of 150µmpitch micro-bumps on the top and 1.0 mm land grid array ( L GA) pad design on the bottom of the package . Th e m aj or ch a ll eng e s th at C PO testing must overcome are: 1) fine pitch, 2) high power, 3) high speed, and 4) a wide temperature range from ro

FAQs

What is the purpose of the double-sided probing system for 150µm-pitch CPO?

It is designed to probe both the top micro-bump sites and the bottom LGA pads of a 150µm-pitch co-packaged optics package with precise alignment while supporting high-speed and thermally stable testing.

Which main testing challenges must the system overcome?

The system must handle fine pitch alignment differences, high power dissipation (up to 600W), high-speed testing (up to 112Gbps), and a wide temperature range from room temperature to 105ºC with thermal expansion control.

How does the proposed approach address reliability during probing?

It proposes a highly integrated probing system using a stable 150µm WLCSP probe within a comprehensive thermal chuck design, aiming for stable contact despite reflected forces and thermal gradients.

Nov 2, 2026

Uploaded by Melati