Concurrent Parallel XIP Flash and SRAM Design for Code Download and Execution on High-Performance Microcontrollers - Design Guide

Oct 28, 2026

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Design guide for the TI TM4C129x microcontrollers that extends the executable memory space by adding concurrent parallel XIP Flash and asynchronous SRAM using a 60-MHz External Peripheral Interface (EPI) in Host-Bus 16 mode. Describes hardware interface requirements, system and block diagrams, and example software. Provides design resources and files such as schematics, BOM, layer plots, Altium/Gerber files, and reference example codes for a parallel flash/SRAM solution with the TM4C1294NCPDT-connected LaunchPad.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages25

Reading Time1 h 3 min

AccessFree to download

System Description

TM4C1294NCPDT

Block Diagram

Getting Started Hardware

Table 1. EPI Interface Option

Flash Memory Card

TI Designs Concurrent Parallel XIP Flash and SRAM Design for Code Download and Execution on High-Performance Microcontrollers Design Guide TI Designs TI Designs provide the foundation that you need including methodology, testing, and design files to quickly evaluate and customize the system. TI Designs help you accelerate your time to market. Design Resources TIDMTM4CFLASHSRAM EK-TM4C1294XL TM4C1294NCPDT TM4C123GH6PMTPD4S012 TPS2052B TPS62177 TPS73733-Q1 SN74LV373A Tool Folder Containing Design Files Tool Folder Product Folder Product Folder Product Folder Product Folder Product Folder Product Folder Product Folder Design Features • Extend the Useable Memory Space to 1-Gbit 16-bit FLASH and 16-Mbit 16-bit Asynchronous SRAM with the 60-MHz External Peripherial Interface (EPI) for Large Memory Footprint Applications • Designed for (formerly Tiva MCU) EKTM4C1294XL Connected LaunchPad ™ • Implements Serial Boot Loader for Programming Parallel Flash In Situ Over EPI • Supports Detection of Flash and SRAM Connected to EPI • Scalable Flash Footprint Design from 64 Mbit to 1 Gbit • Source Code Contains Project Examples for Code Composer Studio Featured Applications • Interactive Human Machine Interfaces • Industrial Automation • IoT Solutions • Test and Measurement | 1-GBit 16-bit
Flash (CS0) | | Single
49x2 Connector | EPI | TM4C1294NCPDT | 10/100 Ethernet | | --- | --- | --- | --- | --- | --- | | 64-MBit 16-bit
SRAM (CS1) | | | Interface | | | An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. All trademarks are the property of their respective owners. TIDU960–May 2015 Concurrent Parallel XIP Flash and SRAM Design for Code Download and 1 Submit Documentation Feedback Execution on High-Performance Microcontrollers Design Guide Copyright © 2015, Texas Instruments Incorporated System Description [www.ti.com](www.ti.com) | 1 | System Description
The TM4C129x family can extend its memory space when the internal memory is insufficient. This design guide describes the hardware interface requirements and example software for the TM4C129x microcontrollers from TI. The executable memory region is extended to 1-Gbit 16-bit FLASH and 16-Mbit 16-bit asynchronous SRAM with the 60-MHz External Peripherial Interface (EPI) operating in Host-Bus 16 Mode. Customer applications can leverage extended memory capabilities of TM4C129 product family. The design files include schematics, BOM, layer plot, Altium files, Gerber files, and reference example codes for easy-to-use parallel asynchronous Flash and SRAM with the TM4C1294NCPDT-connected LaunchPad ™ . | | --- | --- | | 1.1 | TM4C1294NCPDT
TM4C1294NCPDT is a 120-MHz high-performance microcontroller with 1MB on-chip Flash and 256KB onchip SRAM. This microcontroller features an integrated Ethernet MAC+PHY for connected applications. The device has high bandwidth interfaces such as the memory controller and a high-speed USB 2.0 digital interface. With the integration of a number of low-to mid-speed serial communication interfaces like I2C, UART, and SSI; up to 4 MSPS 12-bit ADC; and motion control peripherals, the TM4C1294NCPDT assists in many applications ranging from industrial communication equipments to Smart Grid & Energy applications. | 2 Concurrent Parallel XIP Flash and SRAM Design for Code Download and TIDU960–May 2015 Execution on High-Performance Microcontrollers Design Guide Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated [www.ti.com](www.ti.com) System Description Figure 1. TM4C1294NCPDT Microcontroller High-Level Block Diagram TIDU960–May 2015 Concurrent Parallel XIP Flash and SRAM Design for Code Download and 3 Submit Documentation Feedback Execution on High-Performance Microcontrollers Design Guide Copyright © 2015, Texas Instruments Incorpor

FAQs

What does the design guide enable for TM4C129x microcontrollers?

It enables extending the executable memory space by interfacing parallel 16-bit Flash and 16-bit asynchronous SRAM through the EPI (Host-Bus 16 mode).

Which memory capacities are supported by the Flash memory card?

The Flash memory card supports Flash memory options from 8-Mbit up to 1-Gbit in 16-bit mode, with pin compatibility across the TSSOP package.

What EPI interface frequencies are listed for different configurations?

The guide lists maximum EPI frequencies ranging from 60 MHz for single configurations to lower values for memory configurations with multiple chip selects, such as 40 MHz for 2 chip selects and 20 MHz for 4 chip selects.

Oct 28, 2026

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