Compressed SPICE-Compliant IC Models via Machine Learning Kernel Regression

Aug 3, 2026

This paper presents a fully behavioral machine learning methodology to generate compact, accurate models of IC buffers. The method uses a vector-valued implementation of kernel Ridge regression, building models from measured transient responses collected during normal device operation. It focuses on an efficient compression strategy that reduces model complexity by lowering the number of regression coefficients. The resulting compact representation can be integrated into SPICE-based solvers to support fast signal-integrity and high-speed channel analysis.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages4

Reading Time10 min

AccessFree to download

Abstract

Index Terms

I. Introduction

II. IC Modeling via Kernel Ridge Regression

POLITECNICO DI TORINO Repository ISTITUZIONALE Compressed SPICE-Compliant IC Models via Machine Learning Kernel Regression Original Compressed SPICE-Compliant IC Models via Machine Learning Kernel Regression / Atlante, Marco; Trinchero, Riccardo; Bradde, Tommaso; Manfredi, Paolo; Stievano, Igor S.. -ELETTRONICO. - (2024), pp. 1-3. (Intervento presentato al convegno IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) tenutosi a Bangalore (Ind) nel 17-19 December 2024) [10 . 1109/edaps64431 .2024. 10988464] . Availability: This version is available at: 11583/3000088 since: 2025-05-13T07:35:41Z Publisher: IEEE Published DOI:10.1109/edaps64431.2024.10988464 Terms of use: This article is made available under terms and conditions as specified in the corresponding bibliographic description in the repository Publisher copyright IEEE postprint/Author's Accepted Manuscript ©2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collecting works, for resale or lists, or reuse of any copyrighted component of this work in other works. (Article begins on next page) 04 October 2025 Compressed SPICE-compliant IC Models via Machine Learning Kernel Regression Marco Atlante 1 Dept. Electronics and Telecomm. Politecnico di Torino Torino, Italy marco.atlante@polito.it Riccardo Trinchero2 Dept. Electronics and Telecomm. Politecnico di Torino Torino, Italy riccardo.trinchero@polito.it Tommaso Bradde3 Dept. Electronics and Telecomm. Politecnico di Torino Torino, Italy tommaso.bradde@polito.it Paolo Manfredi4 Dept. Electronics and Telecomm. Politecnico di Torino Torino, Italy paolo.manfredi@polito.it Igor S. Stievano5 Dept. Electronics and Telecomm. Politecnico di Torino Torino, Italy igor.stievano@polito.it Abstract—This paper introduces a fully behavioral machine learning methodology for generating compact and accurate models of IC buffers. The proposed approach leverages a vectorvalued implementation of the kernel Ridge regression to construct models based on observations of device transient responses recorded during normal operation. A key focus is placed on developing an efficient compression scheme to minimize model complexity (i.e., the number of regression coefficients), resulting in a compact mathematical representation that can be efficiently integrated into any SPICE-based solver. Index Terms—digital integrated circuits, buffer modeling, signal integrity, high-speed interconnects, kernel regression. I. INTRODUCTION For decades, the signal and power integrity community has focused on the development of accurate and efficient simulation models of digital IC buffers to be used for the quality and reliability assessment of high-speed digital channels. This trend has been largely driven by the development of the Input/Output Buffer Information Specification (IBIS), supported by electronic design automation (EDA) tools and silicon vendors [1] . IBIS promotes a modeling approach based on fundamental building blocks representing the functionalities of key elements within IC buffers. Despite the widespread adoption of IBIS, the research community has continued to explore alternative solutions aimed at enhancing accuracy and/or simplifying the model generation process [2]–[4] . With the rapid advancement of machine learning (ML) techniques, behavioral modeling approaches for IC buffers based on recurrent neural networks (RNNs) have gained significant attention due to their structural flexibility and accuracy [5],[6] . On the other hand, the training of such kind of model can be computationally expensive, since it requires the solution of anon-convex optimization problem and the tuning of several hyperparameters (e.g., number of layer, number of neuron, etc...) . Moreover, due to their i

FAQs

What problem does the paper address?

It addresses generating accurate and efficient simulation models of IC buffers that can be used in SPICE-based workflows for signal and power integrity analysis.

How does the proposed modeling method work?

It builds a behavioral model using vector-valued kernel Ridge regression trained on observations of the IC port transient responses collected during normal operation.

What is the main contribution regarding model complexity?

It proposes an efficient compression scheme that reduces the number of regression coefficients, producing a compact model representation suitable for integration into SPICE compliant solvers.

Aug 3, 2026

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