Co-Packaged Optics Integration for Hyperscale Networking

Nov 2, 2026

Co-packaged optics (CPO) integrates high-bandwidth optical engines alongside compute chips on the same substrate to improve data-center networking efficiency. It targets higher bandwidth and lower latency while reducing overall system power versus traditional pluggable transceivers. By using silicon photonics optical engines and established semiconductor fabrication processes, CPO aims to improve integration, scale, reliability, and cost. Adoption depends on overcoming assembly, optical coupling, mechanical and thermal design challenges, and validating long-term reliability, serviceability, and interoperability.

LanguageEnglish

CategoryTechnology

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Pages6

Reading Time15 min

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Introduction

Co-Packaged Optics Development

Co-Packaged Optics Integration for Hyperscale Networking Sandeep Razdan 1, Matt Traverso, and Anthony Torza, Cisco Systems, Inc. 1Senior Member IEEE Abstract Co-packaged Optics (CPO) is an emerging technology that integrates high bandwidth optical engines next to a compute chip on the same substrate. The technology’s key advantage lies in the ability to provide high bandwidth [1, 10] and lower latency [18] while reducing overall system power consumption compared to traditional pluggable optical transceivers [1] . By leveraging silicon photonicsbased optical engines, CPO achieves high level of optical and electrical device integration, using proven semiconductor fabrication technologies and design processes, thereby achieving scale, reliability, and cost reduction. However, critical challenges in assembly, optical coupling, mechanical and thermal design must be addressed to ensure reliable and scalable manufacturing. Demonstrating long term reliability, serviceability and interoperability are critical to wide scale adoption and deployment of CPO in hyperscale networks and highperformance computing applications. Introduction Web scale data centers and cloud service providers today handle massive amounts of data traffic that is growing ata rapid pace due to high bandwidth applications such as AI/ML (Artificial Intelligence/Machine Learning), highresolution video streaming and AR/VR (Augmented Reality/Virtual Reality) . Handling such massive amounts of data is expensive, complex, and requires lots of orchestration between networking, server/compute, and memory. This, in turn, is driving increasing demands on network & memory bandwidth, resulting in doubling the aggregate bandwidth of Switch systems/ASICs (Application Specific Integrated Circuits) and Optics every two to three years. Figure 1 below depicts the relative trends in ASIC and Ethernet optics bandwidth scaling over last several years [1, 2] . However, unlike Moore’s law scaling, the increase in bandwidth density results in increasing power requirements for each successive generation. Typical data centers are built with fixed electrical power budgets & energy use forecasts, hence this scaling in bandwidth needs to be within strict power envelopes or require expensive upgrades in infrastructure. Figure 1 ASIC and Ethernet bandwidth evolution with time depicting (a) ASIC bandwidth doubling roughly every 2 years, and (b) Ethernet speeds scaling with ASIC bandwidth. While the compute space drives a lot of efficiencies in silicon architecture, design and software, the networking bottlenecks remain thermal & power optimization (as well as cost reduction) with each successive technology generation. Figure 2a and 2b show these trends for high bandwidth switch systems, with significant contributions from optics toward total system power as well as cost [1, 3] . Figure 2 (a) Optical Interconnects represent ~80% of total switch system cost at higher data rates [3] and (b) Optical Systems represent~50% of total system power for 51.2T systems [1]. As is evident, a large amount of system power and cost goes into moving bits from one part of the data center to another [1] . Even for AI/ML clusters, system bandwidth and latency between GPU/CPU, Memory and Networking interconnects forms a big part of system performance, power, and cost [4, 5, 18] . There are various efforts ongoing in the industry to optimize interconnect & Serdes (SerializationDeserialization) power across switch systems – these include power efficient Serdes design by shrinking silicon nodes, low loss PCB materials, low loss flyover cables as interconnects, linear pluggable optics, as well as CoPackaged Optics (CPO) [6-8] . CPO optimizes power consumption by bringing Optical transceivers closer to the ASIC chips, thereby eliminating retimers and Optics DSPs, and enabling use of low power Serdes options (e.g., XSR & VSR Serdes) [9, 10] . Figure 3 below depicts various architectural choices a

FAQs

What technology does CPO integrate, and why is it beneficial for hyperscale networks?

CPO integrates high-bandwidth optical engines next to compute chips on the same substrate. It improves bandwidth and latency while reducing system power compared with traditional pluggable optics.

How does CPO reduce power consumption compared with traditional pluggable optics?

CPO brings the optical transceivers closer to the ASIC, eliminating retimers and optical DSPs. It also enables lower-power SerDes options such as XSR and VSR.

What challenges must be solved to enable reliable and scalable CPO manufacturing?

Key challenges include assembly, optical coupling, and mechanical and thermal design. Long-term reliability, serviceability, and interoperability are also critical for wide adoption.

Nov 2, 2026

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