Chiplet3D Pin and Thermal Aware 3D Chiplet Floorplanning via Convolution Embedded MILP

Jul 16, 2026

Upload by Skyler

As Moore’s Law scaling slows down, 3DICs stack multiple active dies vertically to sustain performance, but trapped heat makes temperature a primary design constraint. Floorplanning is the earliest, most cost-effective point to address this, yet prior methods rely on center-based wiring assumptions and simplistic power-derived thermal estimates that misguide optimization. Chiplet3D delivers pin- and thermal-aware floorplanning for two-die 3D-ICs, using exact pin coordinates and a convolution-embedded MILP thermal field validated by golden 3D-ICE simulations, reducing average wirelength and peak temperatures while improving thermal uniformity.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages8

Reading Time20 min

Introduction

3D-IC motivation and thermal challenges

Why floorplanning matters

Prior thermal-aware floorplanning approaches

Limitations of existing methods

Chiplet3D overview and contributions

Chiplet3D: Pin- and Thermal-Aware 3D Chiplet Floorplanning via Convolution-Embedded MILP Shuo Ren, Libo Shen, Yaohui Han, Rongliang Fu, Junying Huang, Bei Yu and Tsung-Yi Ho arXiv :2607 .09742v 1 [ cs .AR] 3 Jul 2026 Abstract—As traditional Moore’s Law scaling slows down, 3DICs stack multiple active dies vertically to sustain performance scaling. However, this vertical stacking traps heat inside, making temperature a design concern. Although we can fix thermal issues at different design steps, floorplanning is the earliest and most cost-effective stage to solve it. Previous methods handle this by assuming wires connect to block centers and estimating temperature through simplistic power-based calculations, but these assumptions mislead their wirelength optimization and leave hotspots unresolved. To address these limitations, we present Chiplet3D, a pin- and thermal-aware floorplanner for two-die 3D-ICs. To achieve pin-awareness, it supports all four rotationsand two flips, measuring wirelength from exact pin locations so the solver can flip or rotate blocks to pull connected pins closer. On the thermal side, Chiplet3D replaces the inaccurate powerbased metrics of prior work with a fast, coarse convolution field embedded directly in a mixed-integer linear program (MILP) to accurately track the true 3D heat spread. We evaluate Chiplet3D on the ICCAD’24 ATPlace benchmarks, validating every temperature with a golden 3D-ICE simulation. Chiplet3D reduces wirelength by 39%–43% on average (and up to 62% in the best case), while lowering peak temperatures by up to 45.9◦ Cand reducing thermal non-uniformity by up to 56% compared to the SOTA baselines. Overall, these results demonstrate that by co-optimizing pin alignment and thermal fields, Chiplet3D establishes a stronger Pareto frontier between thermal-aware layout and interconnect efficiency. I. INTRODUCTION As semiconductor technology approaches the physical limits of planar scaling [1], [2], three-dimensional integrated circuits (3D-ICs) have emerged as a key way to keep performance scaling [3] . By vertically integrating functional dies with 3D interconnect technologies [4], [5], 3D-ICs shorten global interconnects and raise integration density [6],[7] . The approach is no longer experimental: commercial parts such as AMD’s 3D V-Cache [8](Fig. 1, left), TSMC’s SoIC [9], and Intel’s Foveros [10], together with interconnect standards like UCIe [11], have made vertical stacking a mainstream option for high-performance systems [12]–[15] . This increase in integration density, however, traps heat: stacked dies leave few escape paths [16], so heat builds up in the interior layers [16]–[19], and heterogeneous stacks that press a high-power compute die against memory or I/O tiles develop steep temperature gradients. The resulting hotspots raise leakage [20], [21], degrade timing [22], [23] and reliability [24], and force chips to throttle below their target frequency [20], [22], [25] . Therefore, 3D floorplanning represents the earliest and most cost-effective stage in 3D-IC design to tackle these thermal issues. This single stage simultaneously determines Fig. 1: Left: AMD’s 3D V-Cache [8] illustrates a commercial stacked-die product. Right: 3D chiplet floorplanning model. die-to-die vertical overlap, lateral spacing between hot blocks, and inter-layer power balance, all while safeguarding high system performance by minimizing interconnect length [26],[27] . Consequently, a good 3D floorplanner must co-optimize both wirelength and temperature. Researchers have made extensive efforts in thermal-aware floorplanning for 3D-ICs. Early work focused on monolithic integration flows for stacking existing 2D IP blocks [28] . Subsequent fixed- and freeoutline methods have increasingly co-optimized interconnect cost with layer assignment, TSV planning, and thermal objectives [26], [27], [29], [30] . Recent flows have extended these goals to heterogeneous chiplet integration and mu

FAQs

Why is 3D floorplanning considered the earliest and most cost-effective stage for thermal issues?

Because it simultaneously determines die-to-die vertical overlap, lateral spacing between hot blocks, and inter-layer power balance, while minimizing interconnect length. Fixing thermal effects at later stages is less effective than optimizing these coupled factors early.

How does Chiplet3D improve connectivity modeling compared with center-based approaches?

Chiplet3D measures wirelength from true pin locations and updates HPWL under allowed rotations and flips. This lets the MILP optimizer directly pull connected pins closer instead of relying on block-center approximations.

What thermal modeling technique does Chiplet3D use inside the MILP?

Chiplet3D replaces inaccurate power-based metrics with a fast, coarse convolution field embedded directly in the MILP. This enables more accurate 3D heat-spread tracking during optimization rather than only verifying hotspots after placement.

Jul 16, 2026

Upload by Skyler