C8051F040/1/2/3/4/5/6/7 - Analog Peripherals - 12/10-Bit SAR ADC and On-Chip Debug

Sep 22, 2026

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C8051F040/1/2/3/4/5/6/7 analog peripheral features and system capabilities are summarized, including 10- or 12-bit SAR ADC options with guaranteed no missing codes, programmable throughput up to 100 ksps or 500 ksps, and support for single-ended or differential inputs. The family provides a SW programmable high-voltage difference amplifier, selectable amplifier gain, windowed interrupt generation, built-in temperature sensing, 8-bit SAR variants, and dual 12-bit DAC synchronization. On-chip debug via JTAG and boundary scan supports breakpoints, single-stepping, watchpoints, and memory/register inspection.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages320

Reading Time13 h 26 min

AccessFree to download

Table of Contents

System Overview

Absolute Maximum Ratings

Global DC Electrical Characteristic

Pinout and Package Definitions

12-Bit ADC (ADC0, C8051F040/1 Only)

10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)

C8051F040/1/2/3/4/5/6/7 8K ISP FLASH MCU Family Analog Peripherals - 10 or 12-Bit SAR ADC • 12-bit (C8051F040/1) or 10-bit (C8051F042/3/4/5/6/7) resolution • ± 1 LSB INL, guaranteed no missing codes • Programmable throughput up to 100 ksps • 13 External Inputs; single-ended or differential • SW programmable high voltage difference amplifier • Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 • Data-dependent windowed interrupt generator • Built-in temperature sensor - 8-bit SAR ADC (C8051F040/1/2/3 only) • Programmable throughput up to 500 ksps • 8 External Inputs, single-ended or differential • Programmable amplifier gain: 4, 2, 1, 0.5 - Two 12-bit DACs (C8051F040/1/2/3 only) • Can synchronize outputs to timers for jitter-free waveform generation - Three Analog Comparators • Programmable hysteresis/response time - Voltage Reference - Precision V DD Monitor/Brown-Out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full-speed, nonintrusive in-circuit/in-system debugging - Provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - IEEE1149 .1 compliant boundary scan - Complete development kit High-Speed 8051 μC Core - Pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - 20 vectored interrupt sources Memory - 4352 bytes internal data RAM (4 k + 256) - 64 kB (C8051F040/1/2/3/4/5) or 32 kB (C8051F046/7) Flash; in-system programmable in 512-byte sectors - External 64 kB data memory interface (programmable multiplexed or non-multiplexed modes) Digital Peripherals - 8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant - 4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant - Bosch Controller Area Network (CAN 2.0B), hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial ports available concurrently - Programmable 16-bit counter/timer array with 6 capture/compare modules - 5 general purpose 16-bit counter/timers - Dedicated watch-dog timer; bi-directional reset pin Clock Sources - Internal calibrated programmable oscillator: 3 to 24.5 MHz - External oscillator: crystal, RC, C, or clock - Real-time clock mode using Timer 2, 3, 4, or PCA Supply Voltage: 2.7 to 3.6 V - Multiple power saving sleep and shutdown modes 100-Pin and 64-Pin TQFP Packages Available - Temperature Range: –40 to +85 °C Rev. 1.7 10/22 Copyright © 2022 by Silicon Laboratories C8051F040/1/2/3/4/5/6/7 C8051F040/1/2/3/4/5/6/7 2 Rev. 1.7 C8051F040/1/2/3/4/5/6/7 Table of Contents 1. System Overview .................................................................................................... 19 1.1. CIP-51™ Microcontroller Core .......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 26 1.2. On-Chip Memory ............................................................................................... 27 1.3. JTAG Debug and Boundary Scan..................................................................... 28 1.4. Programmable Digital I/O and Crossbar ........................................................... 29 1.5. Programmable Counter Array ........................................................................... 30 1.6. Controller Area Network .................................................................................... 31 1.7 . Serial Ports ..........................................................................................

FAQs

What SAR ADC resolution and throughput options are provided in this MCU family?

The device family includes 10- or 12-bit SAR ADC options. It supports programmable throughput up to 100 ksps for the 12-bit configuration and up to 500 ksps for the 8-bit SAR ADC variant on C8051F040/1/2/3.

How do the analog inputs and amplification work for ADC measurements?

Inputs support single-ended or differential configurations. A SW programmable high-voltage difference amplifier is included with selectable programmable gain values, and ADC0 includes an analog multiplexer and PGA.

What debug capabilities are available on-chip?

On-chip debug circuitry provides full-speed, nonintrusive in-circuit/in-system debugging through JTAG and boundary scan. It includes breakpoints, single-stepping, watchpoints, and the ability to inspect or modify memory and registers.

Sep 22, 2026

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