AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference

Jul 16, 2026

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Spiking neural networks run on diverse, fragmented hardware ecosystems where fixed neuron models and execution strategies limit portability across workloads. AIGOR introduces a modular, event-driven neuromorphic architecture for SNN inference that organizes timestep-synchronized processing cores exchanging spikes as packetized messages. Parameterized compute, memory, and communication IP blocks are assembled from a single declarative specification, generating cores, neuron kernels, and synaptic-memory images per instance. Validation on AMD Versal VPK180 shows accuracy preservation across distinct workloads and characterizes synchronization and throughput bottlenecks.

LanguageEnglish

CategoryResearch & Report

FormatPDF

Pages21

Reading Time53 min

Abstract

Introduction

Fragmented hardware landscape for SNNs

Retargeting limitations of design-time fixed platforms

AIGOR architecture overview

arXiv :2607 .03 19 1v 1 [ cs .AR] 3 Jul 2026 AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference Pierpaolo Perticaroli∗1, Roberto Ammendola2 , Andrea Biagioni 1 , Ottorino Frezza 1 , Francesca Lo Cicero 1 , Michele Martinelli 1 , Pier Stanislao Paolucci 1 , Elena Pastorelli 1 , Luca Pontisso 1 , Cristian Rossi3,1 , Francesco Simula 1 , Piero Vicini 1 , and Alessandro Lonardo 1 1 Istituto Nazionale di Fisica Nucleare, Sezione di Roma, Rome, Italy 2 Istituto Nazionale di Fisica Nucleare, Sezione di Roma Tor Vergata, Rome, Italy 3 Università Sapienza di Roma, Rome, Italy July 7, 2026 Abstract Spiking neural networks (SNNs) run today on a fragmented landscape of hardware: dedicated neuromorphic processors, applicationspecific FPGA accelerators, and large-scale neuroscience simulators, each typically built around a fixed neuron model, execution strategy, or workload class. We present AIGOR, a modular, event-driven neuromorphic architecture for spiking neural network inference. AIGOR organizes neurons into timestep-synchronized processing cores that exchange spikes as packets over a packet-switched communication layer, and it is assembled from a library of parameterized compute, memory, and communication IP blocks rather than as a one-off design fora single network. The neuron model, numeric precision, the folding of neurons onto hardware, and the partitioning across cores are configured per instance rather than committed at design time; a single declarative specification then generates the cores, neuron kernels, and synaptic-memory images that realize a given network. We validate a first prototype on the AMD Versal VPK180 across two deliberately different workloads mapped onto the same cores: afeedforward image classifier trained in snnTorch and a recurrent balanced random network modeled in NEST. The classifier reproducesits snnTorch reference accuracy, and the recurrent network matches its NEST reference at spike-level precision across multiple cores spanning two FPGAs. We report post-implementation resource utilization ∗ Corresponding authors: [pierpaolo.perticaroli@roma1.infn.it](pierpaolo.perticaroli@roma1.infn.it), [alessandro.lonardo@roma1.infn.it](alessandro.lonardo@roma1.infn.it) and validate the multi-node synchronization scheme in simulation up to one thousand cores on a three-dimensional torus. The prototype’s measured limits localize the throughput bottleneck in the synapticdelivery datapath and the global timestep barrier, and motivate a set of datapath refinements, now in development, that the configurable structure of the architecture admits as changes to the same cores. 1 Introduction Spiking neural networks are studied and deployed across communities with rather different goals and tools. In machine learning, SNNs are pursued asan energy-efficient, event-driven alternative to conventional deep networks [14, 23] and are trained with surrogate-gradient methods [24, 10], often run on dedicated neuromorphic processors [18, 19] or on application-specific accelerators. In computational neuroscience, large recurrent networks are simulated to study brain dynamics [13] on CPU/GPU clusters or on specialized simulation engines [11, 12] . A related strand pursues SNNs for real-time inference at the data source in high-energy-physics experiments [25, 26] . Alongside these sits a broad body of FPGA implementations spanning both worlds. The result is a fragmented landscape with little common ground across neuron models, execution strategies, and workload classes. Many application-specific designs commit a neuron model, a numeric precision, a degree of parallelism, an interconnect, and a connectivity pattern at design time, tailoring the compute logic, the software-ingestion path, and the communication to a single use case. Such designs are effective for their target workload but are not easily retargeted to a different network class. Rigidity is addressed in two est

FAQs

What problem does AIGOR address in current neuromorphic hardware for SNN inference?

It targets the fragmented SNN hardware landscape where fixed neuron models, precisions, and execution strategies make it hard to reuse accelerators across different network classes. AIGOR aims to provide a configurable architecture that can be instantiated for varying workloads.

How does AIGOR structure computation and communication in its architecture?

AIGOR places neurons into processing cores that advance the same discrete timestep together, exchanging spikes as packets over a packet-switched communication layer. Input/output cores connect the system to the external environment.

What validation approach is used and what were the key outcomes on the prototype?

A first prototype is validated on AMD Versal VPK180 with two deliberately different workloads mapped onto the same cores. The feedforward classifier matches snnTorch reference accuracy, and the recurrent network matches NEST reference at spike-level precision while measurements identify throughput and timestep synchronization bottlenecks.

Jul 16, 2026

Upload by Aria