2.9-Mbit field memory with noise reduction - SAA4956TJ - Preliminary specification

Oct 12, 2026

Preliminary specification for the SAA4956TJ integrated-circuit device: a 2.9-Mbit field memory with optional field-based noise reduction. The design targets advanced TV applications such as 100/120 Hz TV, PALplus, PIP, and 3D comb filtering. It provides FIFO continuous and asynchronous read/write modes, random block access during pointer reset, cascade operation for deeper storage or longer delay, and separate 12-bit serial ports controlled with independent clocks. Includes ordering, quick reference parameters, block-diagram architecture, and interface details.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages37

Reading Time1 h 33 min

AccessFree to download

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

Field memory function

Noise reduction function

I2C-bus interface

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount packages

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for wave and reflow soldering methods

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I2C COMPONENTS

INTEGRATED CIRCUITS | DATA SHEET | | --- | | | | SAA4956TJ
2.9-Mbit field memory with noise reduction | Preliminary speciﬁcation 1998 Dec 08 File under Integrated Circuits, IC02 2.9-Mbit ﬁeld memory with noise reduction SAA4956TJ CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Field memory function 7.1.1 Write operation 7.1.2 Read operation 7.1.3 Power-up and initialization 7.1.4 Old and new data access 7.1.5 Memory arbitration logic and self-refresh 7.1.6 Cascade operation 7.1.7 Test mode operation 7.2 Noise reduction function 7.2.1 Reformatting and formatting 7.2.2 Band-splitting 7.2.3 Motion detection 7.2.4 K-factor 7.2.5 Noise shape 7.3 I2C-bus interface 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 APPLICATION INFORMATION 12 PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages 13.2 Reflow soldering 13.3 Wave soldering 13.4 Manual soldering 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I2C COMPONENTS 1998 Dec 08 2 2.9-Mbit ﬁeld memory with noise reduction SAA4956TJ 1 FEATURES • 2949264-bit field memory with optional field based noise reduction • 245772 × 12-bit organization • 3.3 V power supply • Inputs fully TTL compatible when using an extra 5 V power supply • High speed read and write operations • FIFO operations: – Full word continuous read and write – Independent read and write pointers (asynchronous read and write access) – Resettable read and write pointers. • Optional field based noise reduction activated by an enable pin and controlled via the I2C-bus • Optional random access by block function (40 words per block) enabled during pointer reset operation • Quasi static (internal self-refresh and clocking pauses of infinite length) • Write mask function • Cascade operation possible • Compatible with SAA4955TJ • 16-Mbit CMOS DRAM process technology • 40-pin SOJ package. 2 GENERAL DESCRIPTION The SAA4956TJ is a 2949264-bit field memory with an optional field based noise reduction designed for advanced TV applications such as 100/120 Hz TV, PALplus, PIP and 3D comb filter. The SAA4956TJ is functional and pin compatible with the SAA4955TJ. However, the SAA4956TJ has also, in addition to the field memory function, a field based noise reduction circuit. If this function is enabled it can be controlled via the I2C-bus. The maximum storage depth is 245772 words × 12 bits. A FIFO operation with full word continuous read and write could be used as a data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is written once, then read as many times as required as long as new data is not written. In addition to the FIFO operations, a random block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4956TJs can be cascaded to provide a greater storage depth or a longer delay, without the need for additional circuitry. The SAA4956TJ contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read operation can begin. 3 ORDERING INFORMATION

FAQs

What is the SAA4956TJ and what is its main purpose?

The SAA4956TJ is a 2.9-Mbit field memory with an optional field-based noise reduction circuit. It is designed for advanced TV applications such as 100/120 Hz TV, PALplus, PIP, and 3D comb filter processing.

How do FIFO operations work in the SAA4956TJ?

It supports full-word continuous FIFO read/write with resettable read and write pointers. It also supports asynchronous read and write access, enabling the device to multiply data rate by writing once and reading multiple times as long as new data is not written.

How is the optional noise reduction and control interface implemented?

The field-based noise reduction is activated by an enable pin and controlled via the I2C-bus. The chip includes separate 12-bit wide serial ports for reading and writing, with independent clocking to support asynchronous operations.

Oct 12, 2026

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