1Gb 1.8V x1, x2, x4 - SPI NAND Flash Memory Features - Part Numbering Information

Nov 1, 2026

Uploaded by SALUTone

1Gb 1.8V x1/x2/x4 SPI NAND Flash memory feature summary covering SLC technology, page and block organization, plane capacity, and array performance. The document specifies standard and extended SPI-compatible interfaces with configurable instruction/address/data on 1-4 pins, internal ECC support, read/program/erase timing, and advanced read/cache and ID functions. It also describes initialization behavior, security modes including ECC-enabled shipment state and write protection, permanent block locking with OTP space, electrical operating limits, and reliability targets such as endurance and data retention.

LanguageEnglish

CategoryTechnology

FormatPDF

Pages59

Reading Time2 h 29 min

AccessFree to download

General Description

Architecture

Pin Assignments

Pin Descriptions

Memory Mapping

Array Organization

Bus Operation

SPI Modes

SPI Protocols

SPI NAND Command Definitions

RESET Operation

WRITE Operations

WRITE ENABLE (06h)

WRITE DISABLE (04h)

READ Operations

NAND Flash Memory Serial Peripheral Interface (SPI) MT29F1G01ABBFDSF, MT29F1G01ABBFDWB Features • Single-level cell (SLC) technology • 1Gb density • Organization – Page size x1: 2176 bytes (2048 + 128 bytes) – Block size: 64 pages (128K + 8K bytes) – Plane size: 1Gb (1 plane, 1024 blocks per plane) • Standard and extended SPI-compatible serial bus interface – Instruction, address on 1 pin; data out on 1, 2, or 4 pins – Instruction on 1 pin; address, data out on 2 or 4 pins – Instruction, address on 1 pin; data in on 1 or 4 pins • User-selectable internal ECC supported – 8 bits/512 bytes • Array performance – 83 MHz clock frequency (MAX) – Page read: 25µs (MAX) with on-die ECC disabled; 80µs (MAX) with on-die ECC enabled – Page program: 200µs (TYP) with on-die ECC disabled; 220µs (TYP) with on-die ECC enabled – Block erase: 2ms (TYP) • Advanced features – Read page cache mode – Read page cache random – Read parameter page – Read unique ID • Device initialization – Automatic device initialization after power-up • Security – Blocks 7:0 are valid when shipped from factory with ECC enabled – Software write protection with lock register – Hardware write protection to freeze BP bits – Lock tight to freeze BP bits during one power cycle instead of WP\# • Permanent block lock protection – OTP space: 10 pages one-time programmable NAND Flash memory area • Operating voltage range – VCC = 1.7–1.95V • Operating temperature – Industrial: –40°C to +85°C • Quality and reliability – Endurance: 100,000 PROGRAM/ERASE cycles – Data retention: JESD47H-compliant; see qualification report – Additional: Uncycled data retention: 10 years 24/7 @85°C • Package – 16-pin SOP, 300 mils (package code: SF) – 8-pin U-PDFN, 8mm x 6mm x 0.65mm (package code: WB) CCMTD-1725822587-10363 m78a_ 1gb_1_ 8v_nand_spi.pdf – Rev. F 11/16 EN 1 Micron Technology, Inc. reserves the right to change products or specifications © 2015 Micron Technology, Inc. All without notice. rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary 1Gb 1.8V x1, x2, x4: SPI NAND Flash Memory Features Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’[s part catalog search at www.micron.com. To compare features and specifications by device type](s part catalog search at www.micron.com. To compare features and specifications by device type), [visit www.micron.com/products. Contact](visit www.micron.com/products. Contact) the factory for devices not found. Figure 1: Part Number Chart Micron Technology Product Family 29F = NAND Flash memory Density xG = xGb Device Width x = x bits Level A = SLC Classification B = Discrete, 1 chip select Operating Voltage Range A = 3.3V (2 .7–3.6V) B = 1.8V (1 .7–1.95V) Generation Feature Set MT 29F 2G 01 A B A G D 12 IT ES :F Design Revision (shrink) Production Status Blank = Production ES = Engineering sample Special Options Blank Operating Temperature Range IT = Industrial (–40°C to +85°C) AAT = Automotive (–40°C to +105°C) Speed Grade Blank if no speed grade is defined Package Code SF = 16-pin SOP (300 mils) WB = 8-pin U-PDFN (8mm x 6mm x 0 .65mm) 12 = 24-ball T-PBGA (6mm x 8mm) Interface D = SPI CCMTD-1725822587-10363 m78a_ 1gb_1_ 8v_nand_spi.pdf – Rev. F 11/16 EN 2 Micron Technology, Inc. reserves the right to change products or specifications © 2015 Micron Technology, Inc. All without notice. rights reserved. Contents General Description ......................................................................................................................................... 7 Architecture ..............................................................................................................

FAQs

What are the key memory organization parameters for this SPI NAND Flash?

It uses SLC technology with 1Gb density, a page size of 2176 bytes (2048+128), block size of 64 pages (128K+8K bytes), and a plane size of 1Gb (1 plane, 1024 blocks per plane).

How does the device support ECC and what are the read/program timing differences?

It supports user-selectable internal ECC (8 bits/512 bytes). Page read is 25µs max with on-die ECC disabled and 80µs max with ECC enabled; page program is 200µs typical with ECC disabled and 220µs typical with ECC enabled.

What security and write protection features are included?

Blocks 7:0 are valid when shipped with ECC enabled, and it provides software write protection via a lock register plus hardware write protection to freeze BP bits. It also includes permanent block lock protection using OTP space of 10 pages.

Nov 1, 2026

Uploaded by SALUTone