[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-1-en-105":3,"doc-seo-167801-105":53,"doc-detail-167801-en":127},{"code":4,"msg":5,"data":6},0,"success",[7,14,19,24,29,34,39,44,49],{"id":8,"doc_module":9,"doc_module_name":10,"category_name":11,"show_sort_weight":12,"slug":13},11,1,"Template","Presentations",90,"presentations",{"id":15,"doc_module":9,"doc_module_name":10,"category_name":16,"show_sort_weight":17,"slug":18},12,"Resumes",80,"resumes",{"id":20,"doc_module":9,"doc_module_name":10,"category_name":21,"show_sort_weight":22,"slug":23},14,"Invoices",70,"invoices",{"id":25,"doc_module":9,"doc_module_name":10,"category_name":26,"show_sort_weight":27,"slug":28},15,"Posters",60,"posters",{"id":30,"doc_module":9,"doc_module_name":10,"category_name":31,"show_sort_weight":32,"slug":33},16,"Social Media",50,"social-media",{"id":35,"doc_module":9,"doc_module_name":10,"category_name":36,"show_sort_weight":37,"slug":38},17,"Forms",40,"forms",{"id":40,"doc_module":9,"doc_module_name":10,"category_name":41,"show_sort_weight":42,"slug":43},18,"Letters",30,"letters",{"id":45,"doc_module":9,"doc_module_name":10,"category_name":46,"show_sort_weight":47,"slug":48},21,"Paper Templates",5,"papers-templates",{"id":50,"doc_module":9,"doc_module_name":10,"category_name":51,"show_sort_weight":4,"slug":52},158,"General","general-158",{"code":4,"msg":54,"data":55},"ok",{"site_id":56,"language":57,"slug":58,"title":59,"keywords":60,"description":61,"schema_data":62,"social_meta":120,"head_meta":122,"extra_data":124,"updated_unix":126},105,"en","vlsi-lab-template-word","VLSI Lab Template - Word","","ECEN 474/704 lab write-up template outlining how to present lab discussion, simulation evidence, and physical implementation results. The structure guides students to compare final designs with pre-lab versions, explain observed trends from data and pre-/post-layout simulations, and address expectations, trade-offs, specification issues, and potential future improvements. It also specifies where to include result summary tables, sub-circuit and test bench schematics with labeled signals, floor plans and layout images, DRC/LVS verification screenshots, and annotated simulation plots.",{"@graph":63,"@context":119},[64,80,102],{"@type":65,"itemListElement":66},"BreadcrumbList",[67,71,74,77],{"item":68,"name":69,"@type":70,"position":9},"https://docshare.wps.com","Home","ListItem",{"item":72,"name":10,"@type":70,"position":73},"https://docshare.wps.com/template/",2,{"item":75,"name":11,"@type":70,"position":76},"https://docshare.wps.com/template/presentations/",3,{"item":78,"name":59,"@type":70,"position":79},"https://docshare.wps.com/template/vlsi-lab-template-word/167801/",4,{"url":78,"name":59,"@type":81,"image":82,"author":87,"headline":59,"publisher":90,"fileFormat":93,"inLanguage":57,"description":61,"dateModified":94,"datePublished":95,"encodingFormat":93,"isAccessibleForFree":96,"interactionStatistic":97},"DigitalDocument",{"url":83,"@type":84,"width":85,"height":86},"https://docshare.wps.com/thumbnails/vlsi-lab-template-word/167801.png","ImageObject",442,249,{"name":88,"@type":89},"WPS_1786070896","Person",{"url":68,"name":91,"@type":92},"DocShare","Organization","application/vnd.openxmlformats-officedocument.wordprocessingml.document","2026-10-24","2026-08-31",true,{"@type":98,"interactionType":99,"userInteractionCount":101},"InteractionCounter",{"@type":100},"ViewAction",8,{"@type":103,"mainEntity":104},"FAQPage",[105,111,115],{"name":106,"@type":107,"acceptedAnswer":108},"What should be included in the lab discussion section?","Question",{"text":109,"@type":110},"Summarize the lab and results, compare final designs with pre-lab designs, describe major design changes and their reasons, and explain trends or differences in simulation results.","Answer",{"name":112,"@type":107,"acceptedAnswer":113},"What information should be presented in the summary of results?",{"text":114,"@type":110},"Provide one or two tables summarizing simulation results, such as process parameter characterization and a comparison of pre- and post-layout results.",{"name":116,"@type":107,"acceptedAnswer":117},"What evidence is required for DRC and LVS results?",{"text":118,"@type":110},"Include DRC RVE window results for each layout cell filtered to show unresolved violations, and provide LVS report summary images showing NetID, time stamp, and a pass indicator.","https://schema.org",{"og:url":78,"og:type":121,"og:title":59,"og:site_name":91,"og:description":61},"article",{"robots":123,"canonical":78},"index,follow",{"doc_id":125,"site_id":56},167801,1788219709,{"code":4,"msg":5,"data":128},{"doc_id":125,"user_id":129,"nickname":88,"user_avatar":130,"doc_module":9,"category_id":8,"category_name":11,"doc_title":59,"doc_description":61,"doc_content":131,"file_id":132,"file_url":133,"file_type":134,"file_size":135,"view_count":101,"is_deleted":4,"is_public":9,"is_downloadable":9,"audit_status":9,"page_count":73,"language":136,"language_code":57,"site_id":56,"html_lang":57,"table_of_contents":137,"faqs":138,"seo_title":139,"seo_description":61,"update_tm":126,"read_time":9},549768072016,"https://ap-avatar.wpscdn.com/davatar_155a257f0dc6eb9ab79c44ca47cae57d","ECEN 474/704: Lab XX\nLab subtitle (what the lab is about)\nName here\nUIN: XXXXXXXXX\nDue date: yyyy-mm-dd\nI. DISCUSSION OF THE LAB AND RESULTS\nInclude a short write-up (a paragraph or two) summarizing the lab and results. Compare the final designs with your pre-lab designs (as applicable for the lab), and make note of any major changes in your designs and why these changes were made. Regarding the simulation results, briefly describe any trends that are shown from the data or differences between pre- and post-layout simulation results, and attempt to provide an explanation for the trends and/or differences. Additionally, consider some of the following questions: were the results as you expected? Why or why not? What, if any, design trade-offs are demonstrated by the work in the given lab? If you were unable to meet any specifications given in the lab, what do you believe was the primary cause and what could be some potential solutions for the future?\nThe above questions are not an exhaustive list of what could be discussed and may not be relevant for all labs, but rather they serve as a starting point for you to demonstrate your understanding of the lab material.\nII. SUMMARY OF RESULTS\nSummarize the simulation results from the lab in one or two tables, like what is shown below.\nTable 1\nExample summary of results for process parameter characterization\nTable 2\nExample summary table of pre- and post-layout results\nIII. SUB-CIRCUIT AND TEST BENCH SCHEMATICS\nSchematics of the sub-circuit(s) being designed in the lab should be included here. In addition, include images of the test bench schematics. Important signals in the test bench schematic should be labeled to provide clear correspondence between the signals in the schematics and the signals that are plotted in the simulation results shown later in the report.\nIV. LAYOUT(S) AND FLOOR PLAN(S)\nInclude diagrams of the floor plans used to lay out major circuit components. Typically, this will just include transistor floor plans (routing does not need to be included in the diagrams). A table can be used to show the layout arrangement for the transistors or the floor plan can be drawn in another software tool. Clearly label the devices in the floor plan and make sure there is clear correspondence with the devices in the schematics, and include dummy devices in the floor plan diagram (dummy devices are often denoted with an asterisk, *).\nThis section will also include images of the layout(s) of each circuit constructed for the lab.\nV. DRC AND LVS RESULTS\nThis section should include the DRC RVE window results for each layout cell (with the results filtered to “show unresolved” to show only the remaining DRC violations), and the cell name should be visible at the top of the DRC RVE window. The LVS report summary image should also be included for each cell with your NetID, the time stamp, and the smiley face/check mark visible to show that LVS passed.\nVI. SIMULATION RESULTS\nImages of simulation results requested in the lab manual should be included here. Plots should be annotated to show relevant data points which will include either (1) data points that are explicitly requested in the lab manual or (2) data points from which other requested parameters are calculated. Data in the images should also be legible, so scale the images accordingly to make sure the data is easy to read. Post-layout simulations should be plotted in the same window with the pre-layout simulation results in order to make the differences between the two more apparent.","cbCaigQ27AxzfybW","https://ap.wps.com/l/cbCaigQ27AxzfybW","docx",19824,"English","# I. Discussion of the Lab and Results\n## II. Summary of Results\n## III. Sub-Circuit and Test Bench Schematics\n## IV. Layout(s) and Floor Plan(s)\n## V. DRC and LVS Results\n## VI. Simulation Results","[{\"question\":\"What should be included in the lab discussion section?\",\"answer\":\"Summarize the lab and results, compare final designs with pre-lab designs, describe major design changes and their reasons, and explain trends or differences in simulation results.\"},{\"question\":\"What information should be presented in the summary of results?\",\"answer\":\"Provide one or two tables summarizing simulation results, such as process parameter characterization and a comparison of pre- and post-layout results.\"},{\"question\":\"What evidence is required for DRC and LVS results?\",\"answer\":\"Include DRC RVE window results for each layout cell filtered to show unresolved violations, and provide LVS report summary images showing NetID, time stamp, and a pass indicator.\"}]","VLSI Lab Template - Word | DOCX"]