[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-seo-385205-105":3,"detail-sidebar-cat-1-en-105":80,"doc-detail-385205-en":126},{"code":4,"msg":5,"data":6},0,"ok",{"site_id":7,"language":8,"slug":9,"title":10,"keywords":11,"description":12,"schema_data":13,"social_meta":73,"head_meta":75,"extra_data":77,"updated_unix":79},105,"en","ufc-functional-coverage-on-risc-v-microcode","uFC - Functional Coverage on RISC-V microcode","","uFC provides functional coverage metrics for RISC-V microcode by building custom verification flows around uCode. The approach quickly generates coverage focused on opcodes, instruction operands, immediate value cases, exception and interrupt handling, corner scenarios, and branch-history behavior. uFC supports coverage-driven regression in simulation frameworks using Python-generated Trace-CSV, and integrates with both UVM and non-UVM testbenches. In reported results, functional coverage improves from 76% to 99.2% by adding constrained-random targeted tests.",{"@graph":14,"@context":72},[15,34,55],{"@type":16,"itemListElement":17},"BreadcrumbList",[18,23,27,31],{"item":19,"name":20,"@type":21,"position":22},"https://docshare.wps.com","Home","ListItem",1,{"item":24,"name":25,"@type":21,"position":26},"https://docshare.wps.com/template/","Template",2,{"item":28,"name":29,"@type":21,"position":30},"https://docshare.wps.com/template/posters/","Posters",3,{"item":32,"name":10,"@type":21,"position":33},"https://docshare.wps.com/template/ufc-functional-coverage-on-risc-v-microcode/385205/",4,{"url":32,"name":10,"@type":35,"image":36,"author":41,"headline":10,"publisher":44,"fileFormat":47,"inLanguage":8,"description":12,"dateModified":48,"datePublished":49,"encodingFormat":47,"isAccessibleForFree":50,"interactionStatistic":51},"DigitalDocument",{"url":37,"@type":38,"width":39,"height":40},"https://docshare.wps.com/thumbnails/ufc-functional-coverage-on-risc-v-microcode/385205.png","ImageObject",442,249,{"name":42,"@type":43},"lilac","Person",{"url":19,"name":45,"@type":46},"DocShare","Organization","application/pdf","2026-10-05","2026-09-24",true,{"@type":52,"interactionType":53,"userInteractionCount":22},"InteractionCounter",{"@type":54},"ViewAction",{"@type":56,"mainEntity":57},"FAQPage",[58,64,68],{"name":59,"@type":60,"acceptedAnswer":61},"What is uFC in this work?","Question",{"text":62,"@type":63},"uFC is a functional coverage methodology for RISC-V microcode built around uCode, designed to measure design quality efficiently.","Answer",{"name":65,"@type":60,"acceptedAnswer":66},"Which types of coverage targets does uFC cover?",{"text":67,"@type":63},"uFC targets all opcodes and instruction operands, positive/negative immediates, exception/interrupt handling, corner cases (e.g., overflow, underflow, DIV-by-0), aligned/unaligned load-store behavior, and branch hit history.",{"name":69,"@type":60,"acceptedAnswer":70},"How were coverage results improved?",{"text":71,"@type":63},"After running the flow with a regression of 1200+ tests, the work reports 76% functional coverage initially, then adding 20 focused constrained-random tests to reach 99.2% coverage.","https://schema.org",{"og:url":32,"og:type":74,"og:title":10,"og:site_name":45,"og:description":12},"article",{"robots":76,"canonical":32},"index,follow",{"doc_id":78,"site_id":7},385205,1791161190,{"code":4,"msg":81,"data":82},"success",[83,88,93,98,102,107,112,117,122],{"id":84,"doc_module":22,"doc_module_name":25,"category_name":85,"show_sort_weight":86,"slug":87},11,"Presentations",90,"presentations",{"id":89,"doc_module":22,"doc_module_name":25,"category_name":90,"show_sort_weight":91,"slug":92},12,"Resumes",80,"resumes",{"id":94,"doc_module":22,"doc_module_name":25,"category_name":95,"show_sort_weight":96,"slug":97},14,"Invoices",70,"invoices",{"id":99,"doc_module":22,"doc_module_name":25,"category_name":29,"show_sort_weight":100,"slug":101},15,60,"posters",{"id":103,"doc_module":22,"doc_module_name":25,"category_name":104,"show_sort_weight":105,"slug":106},16,"Social Media",50,"social-media",{"id":108,"doc_module":22,"doc_module_name":25,"category_name":109,"show_sort_weight":110,"slug":111},17,"Forms",40,"forms",{"id":113,"doc_module":22,"doc_module_name":25,"category_name":114,"show_sort_weight":115,"slug":116},18,"Letters",30,"letters",{"id":118,"doc_module":22,"doc_module_name":25,"category_name":119,"show_sort_weight":120,"slug":121},21,"Paper Templates",5,"papers-templates",{"id":123,"doc_module":22,"doc_module_name":25,"category_name":124,"show_sort_weight":4,"slug":125},158,"General","general-158",{"code":4,"msg":81,"data":127},{"doc_id":78,"user_id":128,"nickname":42,"user_avatar":129,"doc_module":22,"category_id":99,"category_name":29,"doc_title":10,"doc_description":12,"doc_content":130,"file_id":131,"file_url":132,"file_type":133,"file_size":134,"view_count":22,"is_deleted":4,"is_public":22,"is_downloadable":22,"audit_status":22,"page_count":22,"language":135,"language_code":8,"site_id":7,"html_lang":8,"table_of_contents":136,"faqs":137,"seo_title":138,"seo_description":12,"update_tm":139,"read_time":4},3985747861865,"https://ap-avatar.wpscdn.com/davatar_29158cc5080c5b710cf443261637dec0","uFC – Functional Coverage  \non RISC-V microcode  \nAjeetha Kumari Venkatesan  \nAsFigo Technologies  \n1 Introduction  \nRISC-V – a name that sparks innovation all across the globe! Recent market survey indicates RISC-V industry to touch $92B by 2030 . We at AsFigo are driven by opensource and help our customer adopt the same in chip design. In this work, we share our experience of building custom flows based on opensource ecosystem to build reliable, secure systems using RISC-V.  \nSource: SHD Group  \nSpecifically, we have built flows around uCode to measure quality of designs that save customers weeks in their chip design schedules. It build functional coverage metrics quickly from uCode and aptly named as uFC.  \n2 Typical RISC-V uArch – Trireme example  \nTrireme RISC-  \n3 RISC-V ISA & code coverage  \nV Design Platform  \n© Aldec  \n4 Mining microcode for metrics  \nSV FCOV  \nuFC  \n• all opcodes  \n• all instruction operands  \n• positive/negative immediate values  \n• exception and interrupt handling  \n• corner cases (overflow, underflow, DIV-by-0)  \n• aligned/unaligned load/store operations  \n• forward/backward branches  \n• branch hit history  \n• Illegal, hint instructions  \n• privileged CSRs  \n• hazard conditions  \n–RD port conflict  \n5 Integrating uFC into simulation Framework  \nuFC  \nPython script to generate  \nTrace-CSV  \nSupports both UVM and non-  \nUVM TBs  \nWider applications –  \nEmulation, FPGA, Post-Si etc.  \n• Pick intelligent tests  \n• Optimize regression suites  \nApplications  \nRoadmap  \n• Machine Learning to improve test quality  \n• Floating Point support  \n6 uFC-Branch instructions  \n7 Results  \nWe ran this flow at single core level and a subsystem of 8 cores. We generated 412 coverpoints in a single IP setup and with existing regression of 1200+ tests (each running with 10+ random seeds) we achieved 76% functional coverage at first. We then added specific tests to focus on and ended adding 20 focused tests (constrained random) and ran them with 50 seeds each and got 99 .2% coverage.  \nWe have also deployed similar uFV flow on non-RSIC-V processors and hence are confident that this flow suits various classes of designs.  \n8 Conclusion  \nIn summary, our paper contributes to the growing body of research on RISC-V verification methodologies by introducing a novel approach to address the unique challenges associated with verifying microcode. We believe that our custom flow development for microcode functional coverage will serve as a valuable resource for RISC-V Summit Europe  \n9 References  \n[1] RISC-V, The RISC-V Instruction Set Manual Volume I: User-Level ISA.  \n[2] IEEE, Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language (IEEE Std 1800 -2023)  \n[3] IEEE UVM 1800.2  \n[4] [https://pypi.org/project/riscv](https://pypi.org/project/riscv)assembler  \nAcknowledgements  \nWould like to acknowledge the contributions by my colleagues  \n• Deepa Palaniappan  \n• Hemamalini Sundaram  \nContact Information  \nAjeetha Kumari Venkatesan Director of Verification AsFigo Technologies  \n+44 7308 024 192  \n[ajeethak@asfigo.com](ajeethak@asfigo.com)[ ](ajeethak@asfigo.com)[www.asfigo.com](www.asfigo.com)","cbCaitree8CHrQlV","https://ap.wps.com/l/cbCaitree8CHrQlV","pdf",1442393,"English","# Introduction\n# Typical RISC-V uArch – Trireme example\n# RISC-V ISA & code coverage\n# Mining microcode for metrics\n## uFC\n# Integrating uFC into simulation Framework\n# uFC-Branch instructions\n# Results\n# Conclusion\n# References","[{\"question\":\"What is uFC in this work?\",\"answer\":\"uFC is a functional coverage methodology for RISC-V microcode built around uCode, designed to measure design quality efficiently.\"},{\"question\":\"Which types of coverage targets does uFC cover?\",\"answer\":\"uFC targets all opcodes and instruction operands, positive/negative immediates, exception/interrupt handling, corner cases (e.g., overflow, underflow, DIV-by-0), aligned/unaligned load-store behavior, and branch hit history.\"},{\"question\":\"How were coverage results improved?\",\"answer\":\"After running the flow with a regression of 1200+ tests, the work reports 76% functional coverage initially, then adding 20 focused constrained-random tests to reach 99.2% coverage.\"}]","uFC - Functional Coverage on RISC-V microcode | PDF",1790267345]