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Memory accesses are extracted from computational pipelines, redundant intermediate arrays are removed by trading memory traffic for computation, and rewrite rules produce provably correct optimized code with large resource reductions and competitive or improved performance-per-watt.",{"@graph":14,"@context":73},[15,34,56],{"@type":16,"itemListElement":17},"BreadcrumbList",[18,23,27,31],{"item":19,"name":20,"@type":21,"position":22},"https://docshare.wps.com","Home","ListItem",1,{"item":24,"name":25,"@type":21,"position":26},"https://docshare.wps.com/template/","Template",2,{"item":28,"name":29,"@type":21,"position":30},"https://docshare.wps.com/template/presentations/","Presentations",3,{"item":32,"name":10,"@type":21,"position":33},"https://docshare.wps.com/template/reducing-fpga-memory-footprint-of-stencil-codes-through-automatic-extraction-of-memory-patterns/278602/",4,{"url":32,"name":10,"@type":35,"image":36,"author":41,"headline":10,"publisher":44,"fileFormat":47,"inLanguage":8,"description":12,"dateModified":48,"datePublished":49,"encodingFormat":47,"isAccessibleForFree":50,"interactionStatistic":51},"DigitalDocument",{"url":37,"@type":38,"width":39,"height":40},"https://docshare.wps.com/thumbnails/reducing-fpga-memory-footprint-of-stencil-codes-through-automatic-extraction-of-memory-patterns/278602.png","ImageObject",442,249,{"name":42,"@type":43},"8796093062539","Person",{"url":19,"name":45,"@type":46},"DocShare","Organization","application/pdf","2026-11-04","2026-09-15",true,{"@type":52,"interactionType":53,"userInteractionCount":55},"InteractionCounter",{"@type":54},"ViewAction",9,{"@type":57,"mainEntity":58},"FAQPage",[59,65,69],{"name":60,"@type":61,"acceptedAnswer":62},"Why are stencil codes difficult to optimize on FPGAs?","Question",{"text":63,"@type":64},"They often require stencil-window buffering that does not fit in on-chip BRAM, especially for 3-D domains, forcing costly off-chip memory accesses.","Answer",{"name":66,"@type":61,"acceptedAnswer":67},"What optimization does the paper propose?",{"text":68,"@type":64},"A compiler-based, rewrite-rules algorithm extracts stencil memory accesses from deep computational pipelines and removes redundant intermediate arrays by trading DRAM accesses for computation.",{"name":70,"@type":61,"acceptedAnswer":71},"How is correctness ensured for the generated optimized code?",{"text":72,"@type":64},"The method is based on rewrite rules applied to a strict functional representation derived from Fortran, and it generates provably correct optimized code.","https://schema.org",{"og:url":32,"og:type":75,"og:title":10,"og:site_name":45,"og:description":12},"article",{"robots":77,"canonical":32},"index,follow",{"doc_id":79,"site_id":7},278602,1791749446,{"code":4,"msg":82,"data":83},"success",[84,88,93,98,103,108,113,118,123],{"id":85,"doc_module":22,"doc_module_name":25,"category_name":29,"show_sort_weight":86,"slug":87},11,90,"presentations",{"id":89,"doc_module":22,"doc_module_name":25,"category_name":90,"show_sort_weight":91,"slug":92},12,"Resumes",80,"resumes",{"id":94,"doc_module":22,"doc_module_name":25,"category_name":95,"show_sort_weight":96,"slug":97},14,"Invoices",70,"invoices",{"id":99,"doc_module":22,"doc_module_name":25,"category_name":100,"show_sort_weight":101,"slug":102},15,"Posters",60,"posters",{"id":104,"doc_module":22,"doc_module_name":25,"category_name":105,"show_sort_weight":106,"slug":107},16,"Social Media",50,"social-media",{"id":109,"doc_module":22,"doc_module_name":25,"category_name":110,"show_sort_weight":111,"slug":112},17,"Forms",40,"forms",{"id":114,"doc_module":22,"doc_module_name":25,"category_name":115,"show_sort_weight":116,"slug":117},18,"Letters",30,"letters",{"id":119,"doc_module":22,"doc_module_name":25,"category_name":120,"show_sort_weight":121,"slug":122},21,"Paper Templates",5,"papers-templates",{"id":124,"doc_module":22,"doc_module_name":25,"category_name":125,"show_sort_weight":4,"slug":126},158,"General","general-158",{"code":4,"msg":82,"data":128},{"doc_id":79,"user_id":129,"nickname":42,"user_avatar":11,"doc_module":22,"category_id":85,"category_name":29,"doc_title":10,"doc_description":12,"doc_content":130,"file_id":131,"file_url":132,"file_type":133,"file_size":134,"view_count":55,"is_deleted":4,"is_public":22,"is_downloadable":22,"audit_status":22,"page_count":135,"language":136,"language_code":8,"site_id":7,"html_lang":8,"table_of_contents":137,"faqs":138,"seo_title":139,"seo_description":12,"update_tm":140,"read_time":26},8796093062539,"Szafarczyk, R., Nabi, S. W. and Vanderbauwhede, W. (2023) Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns. In: 32nd International Conference on FieldProgrammable Logic and Applications (FPL 2022), Belfast, United Kingdom, 29 August-2 September 2022, pp. 148-152. ISBN 9781665473903 (doi:  10.1109/FPL57034.2022.00033)  \nThere may be differences between this version and the published version. You are advised to consult the published version if you wish to cite from it.  \n[http://eprints.gla.ac.uk/278313/](http://eprints.gla.ac.uk/278313/)  \nDeposited on 1 September 2022  \nEnlighten – Research publications by members of the University of Glasgow  \n[http://eprints.gla.ac.uk](http://eprints.gla.ac.uk)  \nReducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns  \nRobert Szafarczyk  \nSchool of Computing Science University of Glasgow, Glasgow, UK [robert.szafarczyk@glasgow.ac.uk](robert.szafarczyk@glasgow.ac.uk)  \nSyed Waqar Nabi  \nSchool of Computing Science University of Glasgow, Glasgow, UK [syed.nabi@glasgow.ac.uk](syed.nabi@glasgow.ac.uk)  \nWim Vanderbauwhede  \nSchool of Computing Science University of Glasgow, Glasgow, UK [wim.vanderbauwhede@glasgow.ac.uk](wim.vanderbauwhede@glasgow.ac.uk)  \nAbstract—FPGAs are attractive for scientific high-performance computing due to their potential for high performance-per-Watt. Stencil codes in scientific applications are difficult to optimize on FPGAs, because of redundant, non-contiguous memory accesses to relatively low bandwidth DRAM. In this paper, we present an algorithm to aggressively reduce on-chip block RAM (BRAM) and off-chip DRAM utilisation of stencil codes running on FPGAs. The algorithm extracts memory accesses from computational pipelines and removes all redundant intermediate arrays, including those used for stencil buffering, by trading DRAM accesses for computation. The algorithm is based on rewriterules on a strict functional representation derived from Fortran code and generates provably correct, optimized code.  \nTypical FPGA implementations store the stencil window in on-chip shift registers implemented in BRAMs; we use only DRAM and optimize the memory accesses instead. Our approach dramatically reduces BRAM usage so that the domain size is only limited by available DRAM. We report a drop of 78% and 18% in BRAM usage in 3-D and 2-D stencil codes compared to a manual implementation using shift registers while staying competitive in performance or even improving performance-per-Watt.  \nIndex Terms—stencils, compiler rewrite rules, dataflow, HLS  \nI. INTRODUCTION  \nHigh-Level Synthesis (HLS) has made FPGAs more accessible for software developers, making them a viable platform for the acceleration of High-Performance Computing (HPC) workloads, because of the promise of higher energy efficiency. Most existing HPC climate models (and many new ones) are written in Fortran. Fortran is a highly suitable language for domain scientists to express the underlying physics, and the use of Fortran isn’t a problem when targeting supercomputers consisting of CPUs. Porting to GPUs is non-trivial but feasible [15]; porting such code to FPGAs, however, is very challenging. Manually rewriting large code bases in an HLS language is usually not feasible (e.g. the Weather Research and Forecasting Model (WRF) comprises more than a million lines of Fortran code) .  \nWe have developed a Fortran-to-OpenCL compiler primarily targeting GPUs and have adapted it to translate computeintensive legacy Fortran code for acceleration on FPGAs. In our toolchain 1 , we represent compute-intensive stencil-based finite difference codes in an intermediate dataflow functional language (TyTraCL), allowing provably correct transformations at the dataflow level, without changing computations.  \n1[https://github.com/wimvanderbauwhede/RefactorF4Acc](https://github.com/wimvanderbauwhede/RefactorF4Acc)  \nStencils are difficult to optim","cbCaigXbTnixG7Gr","https://ap.wps.com/l/cbCaigXbTnixG7Gr","pdf",302413,6,"English","# Abstract\n# Introduction\n## High-Level Synthesis and Fortran Stencil Codes\n## Toolchain and Functional Dataflow Representation\n# Background & Related Work\n## Vendor HLS Memory Transformations\n## Pipeline Memory Extraction and DSL Approaches","[{\"question\":\"Why are stencil codes difficult to optimize on FPGAs?\",\"answer\":\"They often require stencil-window buffering that does not fit in on-chip BRAM, especially for 3-D domains, forcing costly off-chip memory accesses.\"},{\"question\":\"What optimization does the paper propose?\",\"answer\":\"A compiler-based, rewrite-rules algorithm extracts stencil memory accesses from deep computational pipelines and removes redundant intermediate arrays by trading DRAM accesses for computation.\"},{\"question\":\"How is correctness ensured for the generated optimized code?\",\"answer\":\"The method is based on rewrite rules applied to a strict functional representation derived from Fortran, and it generates provably correct optimized code.\"}]","Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns | PDF",1789510960]