[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-1-en-105":3,"doc-seo-281622-105":53,"doc-detail-281622-en":127},{"code":4,"msg":5,"data":6},0,"success",[7,14,19,24,29,34,39,44,49],{"id":8,"doc_module":9,"doc_module_name":10,"category_name":11,"show_sort_weight":12,"slug":13},11,1,"Template","Presentations",90,"presentations",{"id":15,"doc_module":9,"doc_module_name":10,"category_name":16,"show_sort_weight":17,"slug":18},12,"Resumes",80,"resumes",{"id":20,"doc_module":9,"doc_module_name":10,"category_name":21,"show_sort_weight":22,"slug":23},14,"Invoices",70,"invoices",{"id":25,"doc_module":9,"doc_module_name":10,"category_name":26,"show_sort_weight":27,"slug":28},15,"Posters",60,"posters",{"id":30,"doc_module":9,"doc_module_name":10,"category_name":31,"show_sort_weight":32,"slug":33},16,"Social Media",50,"social-media",{"id":35,"doc_module":9,"doc_module_name":10,"category_name":36,"show_sort_weight":37,"slug":38},17,"Forms",40,"forms",{"id":40,"doc_module":9,"doc_module_name":10,"category_name":41,"show_sort_weight":42,"slug":43},18,"Letters",30,"letters",{"id":45,"doc_module":9,"doc_module_name":10,"category_name":46,"show_sort_weight":47,"slug":48},21,"Paper Templates",5,"papers-templates",{"id":50,"doc_module":9,"doc_module_name":10,"category_name":51,"show_sort_weight":4,"slug":52},158,"General","general-158",{"code":4,"msg":54,"data":55},"ok",{"site_id":56,"language":57,"slug":58,"title":59,"keywords":60,"description":61,"schema_data":62,"social_meta":120,"head_meta":122,"extra_data":124,"updated_unix":126},105,"en","accurate-machine-learning-based-on-chip-router-modeling-abstract-and-key-results","Accurate Machine-Learning-Based On-Chip Router Modeling - Abstract and Key Results","","As multicore chips become widespread, networks-on-chip (NoCs) serve as the scalable interconnect fabric, making early estimates of power, performance, and area critical under tight power constraints. The work presents accurate architecture-level on-chip router cost models built with machine-learning-based regression. Benchmarked against established approaches such as ORION 2.0 and parametric models, the proposed models reduce estimation error by up to 89% on average. The study targets improved design exploration accuracy and better power-delay-area tradeoff decisions.",{"@graph":63,"@context":119},[64,80,102],{"@type":65,"itemListElement":66},"BreadcrumbList",[67,71,74,77],{"item":68,"name":69,"@type":70,"position":9},"https://docshare.wps.com","Home","ListItem",{"item":72,"name":10,"@type":70,"position":73},"https://docshare.wps.com/template/",2,{"item":75,"name":11,"@type":70,"position":76},"https://docshare.wps.com/template/presentations/",3,{"item":78,"name":59,"@type":70,"position":79},"https://docshare.wps.com/template/accurate-machine-learning-based-on-chip-router-modeling-abstract-and-key-results/281622/",4,{"url":78,"name":59,"@type":81,"image":82,"author":87,"headline":59,"publisher":90,"fileFormat":93,"inLanguage":57,"description":61,"dateModified":94,"datePublished":95,"encodingFormat":93,"isAccessibleForFree":96,"interactionStatistic":97},"DigitalDocument",{"url":83,"@type":84,"width":85,"height":86},"https://docshare.wps.com/thumbnails/accurate-machine-learning-based-on-chip-router-modeling-abstract-and-key-results/281622.png","ImageObject",442,249,{"name":88,"@type":89},"Mason","Person",{"url":68,"name":91,"@type":92},"DocShare","Organization","application/pdf","2026-10-23","2026-09-16",true,{"@type":98,"interactionType":99,"userInteractionCount":101},"InteractionCounter",{"@type":100},"ViewAction",7,{"@type":103,"mainEntity":104},"FAQPage",[105,111,115],{"name":106,"@type":107,"acceptedAnswer":108},"Why is early estimation of NoC power, performance, and area important?","Question",{"text":109,"@type":110},"Power becomes a first-order design constraint in multicore chips, so early-stage estimates are crucial for effective design exploration and power-delay-area tradeoff decisions.","Answer",{"name":112,"@type":107,"acceptedAnswer":113},"What is the main limitation of template-based NoC router modeling approaches?",{"text":114,"@type":110},"They require the implemented router microarchitecture to closely match the assumed architecture, and they struggle to capture effects of different implementation flows and configuration interactions.",{"name":116,"@type":107,"acceptedAnswer":117},"How do the proposed machine-learning router models perform compared with existing models?",{"text":118,"@type":110},"The models reduce estimation error by up to 89% on average when compared with ORION 2.0 and parametric models.","https://schema.org",{"og:url":78,"og:type":121,"og:title":59,"og:site_name":91,"og:description":61},"article",{"robots":123,"canonical":78},"index,follow",{"doc_id":125,"site_id":56},281622,1791745248,{"code":4,"msg":5,"data":128},{"doc_id":125,"user_id":129,"nickname":88,"user_avatar":130,"doc_module":9,"category_id":8,"category_name":11,"doc_title":59,"doc_description":61,"doc_content":131,"file_id":132,"file_url":133,"file_type":134,"file_size":135,"view_count":101,"is_deleted":4,"is_public":9,"is_downloadable":9,"audit_status":9,"page_count":47,"language":136,"language_code":57,"site_id":56,"html_lang":57,"table_of_contents":137,"faqs":138,"seo_title":139,"seo_description":61,"update_tm":140,"read_time":73},5909887256941,"https://ap-avatar.wpscdn.com/davatar_9964176cb1d06d4a9deccf72a44ae3dc","Accurate Machine-Learning-Based On-Chip  \nRouter Modeling  \nKwangok Jeong, Student Member, IEEE, Andrew B. Kahng, Fellow, IEEE, Bill Lin, Senior Member, IEEE, and  \nKambiz Samadi, Student Member, IEEE  \nAbstract—As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average.  \nIndex Terms—Machine learning, nonparemetric regression, on-chip networks.  \nI. INTRODUCTION  \nN ETWORKS-ON-CHIPS (NoCs) are emerging as the  \nde facto interconnection fabric of choice for both general-purpose chip multiprocessors (CMPs) [10], [15] and application-specific multiprocessor systems-on-chip (MPSoCs)  \n[5],[13]. With increasing core counts, there is a corresponding increase in communication demands in multicore designs to facilitate high core utilization and the corresponding critical need for high-performance NoCs. With many opposing parameters, effective early-stage design exploration is essential to enable the realization of achievable power-delay-area tradeoffs. Existing architectural estimation methods in the literature can be broadly classified as template-based approaches: in one way or another, these existing methods assume a specific architecture and underlying circuit implementation in their modeling efforts. The template-based estimation approach is exemplified by the widely-used early-stage NoC power estimation tool ORION [16], and its enhanced successor ORION 2 .0 [8] .  \nThe template-based approach has two fundamental limitations. First, for the power and area estimations to be accurate, the actual router microarchitecture used for implementation must closely match the microarchitecture assumed. The second limitation of template-based estimation is the difficulty of  \nManuscript received March 09, 2010; accepted April 16, 2010 . Date of publication May 27, 2010; date of current version September 17, 2010 . This letter draws on preliminary accounts published at ISOCC-09 [7] andASPDAC-10 [9] . This manuscript was recommended for publication by S. K. Shukla.  \nK. Jeong, B. Lin, and K. Samadi are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0409 USA (e-mail: [kjeong@vlsicad.ucsd.edu](kjeong@vlsicad.ucsd.edu), [billlin@ece.ucsd.edu](billlin@ece.ucsd.edu); [ksamadi@ucsd.edu](ksamadi@ucsd.edu)) .  \nA. B. Kahng is with the Department of Computer Science and Engineering, and the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0404 USA (e-mail: [abk@ucsd.edu](abk@ucsd.edu)).  \nColor versions of one or more of the figures in this letter are available online at [http://ieeexplore.ieee.org](http://ieeexplore.ieee.org).  \nDigital Object Identifier 10.1109/LES.2010.2051413  \ncapturing effects of different application-specific integrated circuit (ASIC) implementation flows and flow options.  \nOther template-based approaches are based on parametric models [1], [2], [4], [12] . These approaches also assume aspecific underlying router microarchitecture, requiring the development of new models for different microarchitectures. For parametric models the modeler needs full comprehension of the underlying router microarchitecture in order to come up with a relevant parametric model. Moreover, it is difficult to capture configuration parameter interactions that may gain significance as the design complexity increases. Finally, most existing parametric modeling approaches fail to consider implementation flow parameters in their models.  \nTo quantify the above limitations","cbCaipucwz2csCCM","https://ap.wps.com/l/cbCaipucwz2csCCM","pdf",406275,"English","# Abstract\n# Index Terms\n# Introduction\n## Networks-on-Chips and Motivation\n## Limitations of Template-Based Estimation\n## Proposed Machine-Learning Modeling Paradigm\n## Contributions","[{\"question\":\"Why is early estimation of NoC power, performance, and area important?\",\"answer\":\"Power becomes a first-order design constraint in multicore chips, so early-stage estimates are crucial for effective design exploration and power-delay-area tradeoff decisions.\"},{\"question\":\"What is the main limitation of template-based NoC router modeling approaches?\",\"answer\":\"They require the implemented router microarchitecture to closely match the assumed architecture, and they struggle to capture effects of different implementation flows and configuration interactions.\"},{\"question\":\"How do the proposed machine-learning router models perform compared with existing models?\",\"answer\":\"The models reduce estimation error by up to 89% on average when compared with ORION 2.0 and parametric models.\"}]","Accurate Machine-Learning-Based On-Chip Router Modeling - Abstract and Key Results | PDF",1789567062]