[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-id-113":3,"doc-seo-183515-113":53,"doc-detail-183515-id":128},{"code":4,"msg":5,"data":6},0,"success",[7,13,17,21,25,29,33,37,41,45,49],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},55,"Document","Agama & Spiritualitas",60,"religion-spirituality",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":11,"slug":16},48,"Cerita & Novel","story-novel",{"id":18,"doc_module":4,"doc_module_name":9,"category_name":19,"show_sort_weight":11,"slug":20},56,"Gaya Hidup","lifestyle",{"id":22,"doc_module":4,"doc_module_name":9,"category_name":23,"show_sort_weight":11,"slug":24},51,"Komik","comic",{"id":26,"doc_module":4,"doc_module_name":9,"category_name":27,"show_sort_weight":11,"slug":28},53,"Layanan Kesehatan","healthcare",{"id":30,"doc_module":4,"doc_module_name":9,"category_name":31,"show_sort_weight":11,"slug":32},54,"Penelitian & Laporan","research-report",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":11,"slug":36},49,"Sastra","literature",{"id":38,"doc_module":4,"doc_module_name":9,"category_name":39,"show_sort_weight":11,"slug":40},52,"Teknologi","technology",{"id":42,"doc_module":4,"doc_module_name":9,"category_name":43,"show_sort_weight":11,"slug":44},50,"Ujian","exam",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":47,"show_sort_weight":11,"slug":48},57,"Umum","general",{"id":50,"doc_module":4,"doc_module_name":9,"category_name":51,"show_sort_weight":4,"slug":52},181,"Formulir","formulir",{"code":4,"msg":54,"data":55},"ok",{"site_id":56,"language":57,"slug":58,"title":59,"keywords":60,"description":61,"schema_data":62,"social_meta":121,"head_meta":123,"extra_data":125,"updated_unix":127},113,"id","concepts-and-methodology-of-analog-chip-design","Konsep dan Metodologi Desain Analog Chip","","Dokumen membahas konsep dan metodologi desain analog untuk chip dengan landasan teknologi CMOS. Uraian meliputi struktur MOS serta simbol dan asumsi bulk, jaringan CMOS, rancangan inverter dan gerbang logika, termasuk penggunaan transmission gate. Dokumen juga menjelaskan alur perancangan dari skematik hingga layout, proses pembuatan layout layer-layer, penggunaan VIA dan CONT, serta tahapan pengecekan DRC. Selanjutnya dipaparkan proses simulasi dan analisis pada lingkungan software desain IC, termasuk pengaturan sinyal, pembuatan netlist, simulasi inverter, hingga evaluasi hasil seperti DRC dan LVS.",{"@graph":63,"@context":120},[64,81,103],{"@type":65,"itemListElement":66},"BreadcrumbList",[67,72,75,78],{"item":68,"name":69,"@type":70,"position":71},"https://docshare.wps.com","Home","ListItem",1,{"item":73,"name":9,"@type":70,"position":74},"https://docshare.wps.com/id/document/",2,{"item":76,"name":39,"@type":70,"position":77},"https://docshare.wps.com/id/document/teknologi/",3,{"item":79,"name":59,"@type":70,"position":80},"https://docshare.wps.com/id/document/concepts-and-methodology-of-analog-chip-design/183515/",4,{"url":79,"name":59,"@type":82,"image":83,"author":88,"headline":59,"publisher":91,"fileFormat":94,"inLanguage":57,"description":61,"dateModified":95,"datePublished":96,"encodingFormat":94,"isAccessibleForFree":97,"interactionStatistic":98},"DigitalDocument",{"url":84,"@type":85,"width":86,"height":87},"https://docshare.wps.com/thumbnails/concepts-and-methodology-of-analog-chip-design/183515.png","ImageObject",300,407,{"name":89,"@type":90},"Noah","Person",{"url":68,"name":92,"@type":93},"DocShare","Organization","application/pdf","2026-10-04","2026-09-02",true,{"@type":99,"interactionType":100,"userInteractionCount":102},"InteractionCounter",{"@type":101},"ViewAction",5,{"@type":104,"mainEntity":105},"FAQPage",[106,112,116],{"name":107,"@type":108,"acceptedAnswer":109},"Apa saja konsep dasar MOS dan CMOS yang dibahas?","Question",{"text":110,"@type":111},"Dokumen membahas struktur MOS, simbol transistor MOS, asumsi bulk pada MOS, serta jaringan CMOS sebagai dasar perancangan rangkaian analog. Bagian ini juga mencakup contoh inverter dan gerbang logika.","Answer",{"name":113,"@type":108,"acceptedAnswer":114},"Bagaimana alur perancangan dari skematik sampai layout dijelaskan?",{"text":115,"@type":111},"Dokumen memaparkan tahapan alur desain IC, termasuk pembuatan skematik, implementasi transmission gate bila diperlukan, lalu berlanjut ke proses layout layer-layer. Di dalamnya ada penjelasan mengenai floor planning, placement, routing, serta penggunaan VIA dan CONT.",{"name":117,"@type":108,"acceptedAnswer":118},"Jenis pengecekan apa yang digunakan dalam desain dan bagaimana hasilnya ditangani?",{"text":119,"@type":111},"Dokumen menguraikan pengecekan DRC melalui alur pengecekan, serta memperlihatkan tindak perbaikan ketika ditemukan error. Selain DRC, juga ditampilkan hasil LVS dan pengecekan lain seperti antenna pada proses validasi.","https://schema.org",{"og:url":79,"og:type":122,"og:title":59,"og:site_name":92,"og:description":61},"article",{"robots":124,"canonical":79},"index,follow",{"doc_id":126,"site_id":56},183515,1788353005,{"code":4,"msg":5,"data":129},{"doc_id":126,"user_id":130,"nickname":89,"user_avatar":131,"doc_module":4,"category_id":38,"category_name":39,"doc_title":59,"doc_description":61,"doc_content":132,"file_id":133,"file_url":134,"file_type":135,"file_size":136,"view_count":102,"is_deleted":4,"is_public":71,"is_downloadable":71,"audit_status":71,"page_count":137,"language":138,"language_code":57,"site_id":56,"html_lang":57,"table_of_contents":139,"faqs":140,"seo_title":141,"seo_description":61,"update_tm":127,"read_time":142},8796095462418,"https://ap-avatar.wpscdn.com/avatar/80000253c1241d02b47?x-image-process=image/resize,m_fixed,w_180,h_180&k=1778826106357471780","# Konsep dan Metodologi\n\nDesain AnalogCHIPBertasiskan TeknologiCMOS DisertaiPenggunaan Tool  \nDAFTAR GAMBAR  \nGambar 1.1 Struktur MOS [5]2Gambar 1.2 Simbol Transistor MOS [8]2Gambar 1.3 Asumsi Bulk pada Transistor MOS [8]3Gambar 1.4 Simbol Depletion Mode [8]3Gambar 1.5 Jaringan CMOS [5]4Gambar 1.6 Rangkaian Inverter dari CMOS [5]5Gambar 1.7 Empat Komponen Desain IC6  \nGambar 1.8 Hirarki Alur Konsep Desain CMOS [8]6  \nGambar 1.9 Alur Desain IC Lengkap8  \nGambar 1.10 Alur Desain IC Lengkap9  \nGambar 1.11 Logo Mentor Graphics [14]11  \nGambar 1.12 Logo Cadence [15]11  \nGambar 1.13 Logo Synopsys [16]11  \nGambar 1.14 Logo Mentor Tanner [17]12  \nGambar 1.15 Logo Open Circuit Design [18]12  \nGambar 1.16 Logo Static Free Software [19]13  \nGambar 1.17 Logo AMS [20]14  \nGambar 1.18 Logo STM [21]14  \nGambar 1.19 Logo Global Foundries [22]15  \nGambar 1.20 Logo TSMC [23]15  \nGambar 1.21 Logo CMP[24]16  \nGambar 1.22 Logo MOSIS [25]16  \nDIpIIuai uenyannCa  \nX  \nGambar 1.23 Pabrikasi dalam Wafer(cmp)[13]17Gambar 1.24 Packaging Layout ke CHIP Model DIL18Gambar 2.1 Simbol Transistor MOS(a)NMOS,(b)PMOS [4]19Gambar 2.2 Simbol Transisto MOS dalam Software,20(a)NMOS,(b)PMOSGambar 2.3 Aturan Bulk [4]21Gambar 2.4 Simbol Gerbang Logika Inverter21Gambar 2.5 Skematik Gerbang Logika Inverter22Gambar 2.6 Simbol Gerbang Logika NAND23Gambar 2.7 Skematik Gerbang Logika NAND  \n24Gambar 2.8 Simbol Gerbang Logika NOR24Gambar 2.9 Skematik Gerbang Logika NOR25Gambar 2.10 Simbol Transimision Gate25Gambar 2.11 Skematik TG26Gambar 2.12 Implementasi Transmission Gate27Gambar 2.13 Alur Desain Skematik30Gambar 3.1 Struktur Layer-layer CMOS AMS 0,35 μm [1][5]34Gambar 3.2 Struktur Layout Transistor36Gambar 3.3 Proses Pembuatan Layout Transistor36Gambar 3.4 Struktur PMOS Teknologi AMS 0,35 μm37Gambar 3.5 Struktur NMOS Teknologi AMS 0,35 μm37Gambar 3.6 Struktur Kapasitor Teknologi AMS 0,35 μm38Gambar 3.7 Struktur Resistor Teknologi AMS 0,35 μm39Gambar 3.8 Polygon dalam Desain Layout39Gambar 3.9 Path dalam Desain LayoutGambar 3.10 Layer VIA  \n叶  \n40  \n41  \nGambar 3.11 Implementasi VIA 1 pada M1M2  \nGambar 3.12 Implementasi VIA 2 pada M2M341Gambar 3.13 Implementasi VIA 2 pada M3M4  \n41  \nGambar 3.14 Layer CONT42Gambar 3.15 Layer Implementasi CONT pada M1P142Gambar 3.16 Layer Implementasi CONT pada M1P242Gambar 3.17 Alur Desain Layout43  \nGambar 3.18(a)Floor Planning,(b)Placemment dan (c)Routing4  \nDIPIIIUai ueiyaii Ca  \nxi  \nDaftar Gambor  \nGambar 4.1 Tipe tipe dariLayer[4]48Gambar 4.2 Pengerekan DRCSderhana49Gambar 4.3 Alur Pengecekan DRC50Gambar 5.1 Desktop KDE54Gambar 5.2 Desktop GNOME55Gambar 5.3 Membuka Terminal CLI55Gambar 5.4Terminal CLI56Gambar 5.5Layer-layer CMOSAMS0,35μm57pada Software Mentor GraphicsGambar 5.6Lilnary untuk Standand Cell AMSC35 pada Software58Mentor GraphicsGambar 5.7 Tampilan ICstudio60Gambar 5.8 Design Architect-IC dengan HIT-KIT AMS0,35 μm61Gambar 5.9 Menu Hit-Kit Teknologi AMS 0,35μm62Gambar 5.10 Menu Devices Hit-Kit Teknologi AMS0,35μm63Gambar 5.11 Layar Konfigurasi Transistor MOS63Gambar 5.12 Akses Menu Generik63Gambar 5.13 Proses Mengubah Label Port64Gambar 5.14 Rangkaian Inverter Menggunakan Teknologi64AMS0,35μm  \n656666  \nGambar 5.15 Hasil Cek Skematik 0,35 μm  \nGambar 5.16 Pembuatan Viewpoint Skematik0,35μmGambar 5.17 Hasil Viewpoint pada IC-Studio  \nGambar 5.18 Tampilan Layar Simulasi67  \nGambar 5.19 Tampilan Layar Mode Simulasi67  \nGambar 5.20 Memuat Library Teknologi dalam Simulasi68  \nGambar 5.21 Pengaturan Analisa Transien68  \nGambar 5.22 Pengaturan Sinyal Masukan Menggunakan Tipe Pattem69Gambar 5.23 Pengaturan Sinyal Power VDD dengan Pattern69  \nGambar 5.24 Pengaturan Sinyal Keluaran70  \nGambar 5.25 Netlist70  \nGambar 5.26 Proses Simulasi71  \nGambar5.27 Hasil Simulasi Inverter71  \nGambar 5.28 Tampilan IC-Station72  \nxii  \nGamhar5.29 Menu Ams Devices  \nGambar 5.30 Layar KonfigurasiLayout Transistor MOSGambar5.31 Placement Transistor MOSGambar 5.32 Konfigurasi Bahan untuk PathGambar 5.33 Routing pada LayoutGambar 5.34 Pemilihan Via  \nG","cbCaiaseXinmtNFo","https://ap.wps.com/l/cbCaiaseXinmtNFo","pdf",1883870,6,"Indonesian","# Daftar Gambar\n## Struktur MOS dan Asumsi Bulk\n## Jaringan CMOS, Inverter, dan Gerbang Logika\n## Alur Desain IC\n## Pabrikasi dan Packaging\n## Transistor MOS, Bulk, dan Aturan Desain\n## Transmission Gate dan Alur Desain Skematik\n## Layout Layer-layer CMOS\n## Proses VIA, CONT, dan Floor Planning\n## Alur Pengecekan DRC\n## Lingkungan dan Langkah Simulasi\n## Pembuatan Simbol dan Netlist\n## Contoh Rangkaian Kompleks (Multiplexer)","[{\"question\":\"Apa saja konsep dasar MOS dan CMOS yang dibahas?\",\"answer\":\"Dokumen membahas struktur MOS, simbol transistor MOS, asumsi bulk pada MOS, serta jaringan CMOS sebagai dasar perancangan rangkaian analog. Bagian ini juga mencakup contoh inverter dan gerbang logika.\"},{\"question\":\"Bagaimana alur perancangan dari skematik sampai layout dijelaskan?\",\"answer\":\"Dokumen memaparkan tahapan alur desain IC, termasuk pembuatan skematik, implementasi transmission gate bila diperlukan, lalu berlanjut ke proses layout layer-layer. Di dalamnya ada penjelasan mengenai floor planning, placement, routing, serta penggunaan VIA dan CONT.\"},{\"question\":\"Jenis pengecekan apa yang digunakan dalam desain dan bagaimana hasilnya ditangani?\",\"answer\":\"Dokumen menguraikan pengecekan DRC melalui alur pengecekan, serta memperlihatkan tindak perbaikan ketika ditemukan error. Selain DRC, juga ditampilkan hasil LVS dan pengecekan lain seperti antenna pada proses validasi.\"}]","Konsep dan Metodologi Desain Analog Chip | PDF",9]