[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-160456-en":3,"doc-seo-160456-105":31,"detail-sidebar-cat-0-en-105":92},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":28,"seo_description":14,"update_tm":29,"read_time":30},160456,2336475401981,"Chumphorn","https://ap-avatar.wpscdn.com/avatar/22000c94efd8d5204d?x-image-process=image/resize,m_fixed,w_180,h_180&k=1786935347598174694",8,"Research & Report","VLSI Implementations of Threshold Logic - A Comprehensive Survey","In-depth review of silicon implementations of threshold logic gates, tracing developments across multiple decades and focusing on very-large-scale integration (VLSI). Surveys early MOS threshold logic approaches and details a wide range of VLSI realizations, including capacitive techniques such as switched-capacitor and floating-gate variants, conductance/current implementations using pseudo-nMOS and output-wired-inverters, and numerous differential solutions. Concludes with brief discussion of other implementation directions, including negative-resistance devices and single-electron technologies.","VLSI Implementations of Threshold Logic—A Comprehensive Survey  \nValeriu Beiu, Senior Member, IEEE, José M. Quintana, and María J. Avedillo  \nAbstract—This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutionsand detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOSand output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.  \nIndex Terms—Integrated circuits, neural-network (NN) hardware, threshold logic, very-large-scale integration (VLSI).  \nI. INTRODUCTION  \nRESEARCH on neural networks (NNs) goes back 60 years.  \nThe seminal year for the development of the “science of mind” was 1943, when the article A Logical Calculus of the Ideas Immanent in Nervous Activity by McCulloch and Pitts was published [31] . They introduced the first, very simplified, mathematical model of a neuron operating in an all-or-none fashion: the threshold logic gate (TLG) . It computes the sign of the weighted sum of its inputs  \n  sgn      \n sgn  (1)  \nwith  being the synaptic weight associated to  the  \nthreshold and  the fan-in ofthe TLG.  \nIt did not take very long for a hardware implementation to be developed. In fact, the summing amplifier from [42] precedes even [31] by submission date: May 1, 1941 . It can  \nManuscript received September 15, 2002; revised May 24, 2003 . The work of V. Beiu was supported in part by the Air Force Research Laboratory under Agreement F29601-02-2-0299 . The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the author and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Air Force Research Laboratory or the U.S. government. The work of J. M. Quintana and M. J. Avedillo was sponsored in part by the EU under IST 2001–32358 Project“QUDOS.”  \nV. Beiu is with the School of Electrical Engineer and Computer Science, Washington State University, Pullman, WA 99164-2752 USA (e-mail: [vbeiu@eecs.wsu.edu](vbeiu@eecs.wsu.edu)).  \nJ. M. Quintana and M. J. Avedillo are with the Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica (IMSE-CNM), Universty of Sevilla, Sevilla 41012, Spain (e-mail: [josem@imse.cnm.es](josem@imse.cnm.es); [avedillo@imse.cnm.es](avedillo@imse.cnm.es)).  \nDigital Object Identifier 10.1109/TNN.2003.816365  \nbe considered the first hardware implementation of a TLG. The patent details: “an electrical calculating device  for obtaining the sum of a plurality of electrical voltages” using“an electrical amplifier having a feedback.  by adjustment of the impedances connected in series with the various sources of voltage, any one or more of the sources may be, in effect, multiplied by any desired factor ” (see Fig. 1) . In 1951, Minsky teamed with Edmonds and designed the first 40-neuron “neurocomputer,” Snark [32] . Although it was an electromechanical implementation built of tubes, motors, and clutches, it successfully modeled the behavior of a rat searching for food in a maze. In 1957, Rosenblatt generalized the McCulloch–Pitts neuron inventing the perceptron [40] . During 1957 and 1958, Rosenblatt, together with Wightmanet al., constructed and successfully demonstrated the Mark I Perceptron. The Mark I Perceptron had 512 adjustable weights implemented as an 8  8  8 array of potentiometers. Due to the successful presentation of the Mark I Perceptron, theneurocomputing field became a subject of intensive research. Shortly af","cbCaifVFeEG9bEwn","https://ap.wps.com/l/cbCaifVFeEG9bEwn","pdf",1049052,2,1,27,"English","en",105,"# Introduction\n## Neural networks and threshold logic fundamentals\n## Historical hardware milestones and models\n## Need for updated VLSI threshold-logic reviews","[{\"question\":\"What does the survey focus on in threshold logic gate implementations?\",\"answer\":\"The survey reviews silicon implementations of threshold logic gates and covers VLSI realizations across several decades, emphasizing hardware structures used to implement threshold behavior.\"},{\"question\":\"Which VLSI implementation approaches are discussed?\",\"answer\":\"It discusses capacitive methods (including switched-capacitor and floating-gate variants), conductance/current approaches (such as pseudo-nMOS and output-wired-inverters), and many differential solutions.\"},{\"question\":\"How is the neuron-threshold interpretation evaluated in the paper?\",\"answer\":\"The paper describes testing the threshold model using spike trains generated by Hodgkin–Huxley with stochastic input, showing the threshold model correctly predicts nearly 90% of spikes, supporting the TLG neuron description.\"}]","VLSI Implementations of Threshold Logic - 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