[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-117458-en":3,"doc-seo-117458-105":29,"detail-sidebar-cat-0-en-105":90},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":20,"language":21,"language_code":22,"site_id":23,"html_lang":22,"table_of_contents":24,"faqs":25,"seo_title":26,"seo_description":14,"update_tm":27,"read_time":28},117458,687207022233,"Riley","https://ap-avatar.wpscdn.com/davatar_155a257f0dc6eb9ab79c44ca47cae57d",6,"Technology","Visualization of Machine Learning Accelerators - Honors Poster Presentation","Honors poster presentation outlining a lab infrastructure that visualizes machine learning accelerator object classification and detection on a display. The work targets students in CprE 487 who build accelerators and need an integrated way to observe latency and accuracy under optimization approaches such as pruning, variable-precision, and sparsity. It describes a ZEDBoard-based design with a memory interface and HDMI pipeline, reports a 55-cycle memory transaction latency at 100 MHz, and estimates support up to 111 FPS, enabling evaluation and iterative improvements.","Department of Electrical and Computer Engineering  \nWilliam Zogg Advisor: Dr. Henry Duwe  \nHonors Poster Presentation May 3 rd, 2023  \nVisualization of Machine Learning Accelerators  \nObjectives  \n• Visualize the object classification and detection capabilities of a machine learning (ML) accelerator onto a display.  \n• Develop a framework where students can insert their accelerator implementations and observe performance effects.  \nContext and Vision  \n• Students in CprE 487 undergo a lab where they develop a ML accelerator.  \n• Currently, students can operate on data storage without any visual method of observing the latency and accuracy statistics of different ML accelerator design optimizations such as:  \n• Pruning  \n• Variable-Precision  \n• Sparsity  \n• The lab uses a ZEDboard from Xilinx, an embedded systems FPGA prototyping platform.  \nDesign  \nFuture Work  \n• Add support for other computer vision (CV) applications.  \n• Student outcome survey  \n• QR code below  \n• Fall 2023 TA  \n• Will further work over the summer and following semester to incorporate the memory interface with the HDMI pipeline to display student results.  \n• Ensure that the framework is as lab-ready as possible, with all encompassing tutorials, descriptions, etc.  \n• Improve the total system bandwidth (BW) using a proper implementation of a direct memory access unit  \n(DMA) .  \n• VHDL Pipeline:  \n• Memory transaction unit  \n• HDMI output chain  \n• User-customizable block for ML accelerator  \nConclusion  \n• Developed lab infrastructure including memory interface and a HDMI pipeline.  \n• The ZEDBoard with the current implementation  \nResults  \nThe system has a memory transaction latency of 55 cycles at 100 MHz. This stat in conjunction with an assumption that the accelerator’s input consists of 256x256 8-bit grayscale ImageNET inputs means that it can support up to 111 frames per second (FPS) .  \nsupports performance up to 111 FPS.  \n• Framework lays the foundation for Fall 2023 labs, evaluations, and future improvements.  \nReferences  \n[1]  P. Gysel, M. Motamedi, and S. Ghiasi,‘Hardwareoriented Approximation of Convolutional Neural Networks’, arXiv [cs.CV] . 2016.  \n[2] [https://www.xilinx.com/products/boards-and](https://www.xilinx.com/products/boards-and)kits/1-8dyf-11.html  \n[3] [https://ambolt.io/en/image-classification-and](https://ambolt.io/en/image-classification-and)object-detection/  \n[4]  CprE 487 lecture slides createdby Dr. Duwe","cbCaidzBnKrTqX7t","https://ap.wps.com/l/cbCaidzBnKrTqX7t","pdf",622881,1,"English","en",105,"# Objectives\n## Visualize classification and detection on a display\n## Provide a framework for student accelerator implementations\n# Context and Vision\n## Current limitations without visual latency/accuracy statistics\n## Student lab workflow in CprE 487\n# Design and Future Work\n## Expand to other computer vision applications\n## Integrate memory interface with HDMI pipeline\n## Improve system bandwidth with DMA\n# VHDL Pipeline\n## Memory transaction unit\n## HDMI output chain\n## User-customizable ML accelerator block\n# Results and Conclusion\n## Memory latency and FPS estimation\n## Foundation for future labs and improvements","[{\"question\":\"What does the visualization framework enable students to observe?\",\"answer\":\"It visualizes object classification and detection and provides a way to observe performance effects such as latency and accuracy across accelerator design optimizations.\"},{\"question\":\"Which optimization methods are explicitly mentioned as future evaluation targets?\",\"answer\":\"The poster lists pruning, variable-precision, and sparsity as optimization categories that the lab framework is meant to evaluate visually.\"},{\"question\":\"What performance results are reported for the current implementation?\",\"answer\":\"The system shows a memory transaction latency of 55 cycles at 100 MHz, and under an ImageNet 256x256 8-bit grayscale input assumption it estimates support up to 111 FPS.\"}]","Visualization of Machine Learning Accelerators - Honors Poster Presentation | PDF",1785675953,3,{"code":4,"msg":30,"data":31},"ok",{"site_id":23,"language":22,"slug":32,"title":13,"keywords":33,"description":14,"schema_data":34,"social_meta":85,"head_meta":87,"extra_data":89,"updated_unix":27},"visualization-of-machine-learning-accelerators-honors-poster-presentation","",{"@graph":35,"@context":84},[36,52,67],{"@type":37,"itemListElement":38},"BreadcrumbList",[39,43,47,49],{"item":40,"name":41,"@type":42,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":44,"name":45,"@type":42,"position":46},"https://docshare.wps.com/document/","Document",2,{"item":48,"name":12,"@type":42,"position":28},"https://docshare.wps.com/document/technology/",{"item":50,"name":13,"@type":42,"position":51},"https://docshare.wps.com/document/visualization-of-machine-learning-accelerators-honors-poster-presentation/117458/",4,{"url":50,"name":13,"@type":53,"author":54,"headline":13,"publisher":56,"fileFormat":59,"inLanguage":22,"description":14,"dateModified":60,"datePublished":61,"encodingFormat":59,"isAccessibleForFree":62,"interactionStatistic":63},"DigitalDocument",{"name":9,"@type":55},"Person",{"url":40,"name":57,"@type":58},"DocShare","Organization","application/pdf","2026-09-04","2026-08-02",true,{"@type":64,"interactionType":65,"userInteractionCount":20},"InteractionCounter",{"@type":66},"ViewAction",{"@type":68,"mainEntity":69},"FAQPage",[70,76,80],{"name":71,"@type":72,"acceptedAnswer":73},"What does the visualization framework enable students to observe?","Question",{"text":74,"@type":75},"It visualizes object classification and detection and provides a way to observe performance effects such as latency and accuracy across accelerator design optimizations.","Answer",{"name":77,"@type":72,"acceptedAnswer":78},"Which optimization methods are explicitly mentioned as future evaluation targets?",{"text":79,"@type":75},"The poster lists pruning, variable-precision, and sparsity as optimization categories that the lab framework is meant to evaluate visually.",{"name":81,"@type":72,"acceptedAnswer":82},"What performance results are reported for the current implementation?",{"text":83,"@type":75},"The system shows a memory transaction latency of 55 cycles at 100 MHz, and under an ImageNet 256x256 8-bit grayscale input assumption it estimates support up to 111 FPS.","https://schema.org",{"og:url":50,"og:type":86,"og:title":13,"og:site_name":57,"og:description":14},"article",{"robots":88,"canonical":50},"index,follow",{"doc_id":7,"site_id":23},{"code":4,"msg":5,"data":91},[92,96,100,104,109,112,117,122,127,130,134],{"id":20,"doc_module":4,"doc_module_name":45,"category_name":93,"show_sort_weight":94,"slug":95},"Story & Novel",90,"story-novel",{"id":46,"doc_module":4,"doc_module_name":45,"category_name":97,"show_sort_weight":98,"slug":99},"Literature",80,"literature",{"id":51,"doc_module":4,"doc_module_name":45,"category_name":101,"show_sort_weight":102,"slug":103},"Exam",70,"exam",{"id":105,"doc_module":4,"doc_module_name":45,"category_name":106,"show_sort_weight":107,"slug":108},5,"Comic",60,"comic",{"id":11,"doc_module":4,"doc_module_name":45,"category_name":12,"show_sort_weight":110,"slug":111},50,"technology",{"id":113,"doc_module":4,"doc_module_name":45,"category_name":114,"show_sort_weight":115,"slug":116},7,"Healthcare",40,"healthcare",{"id":118,"doc_module":4,"doc_module_name":45,"category_name":119,"show_sort_weight":120,"slug":121},8,"Research & Report",30,"research-report",{"id":123,"doc_module":4,"doc_module_name":45,"category_name":124,"show_sort_weight":125,"slug":126},9,"Religion & Spirituality",20,"religion-spirituality",{"id":125,"doc_module":4,"doc_module_name":45,"category_name":128,"show_sort_weight":125,"slug":129},"World Cup","world-cup",{"id":131,"doc_module":4,"doc_module_name":45,"category_name":132,"show_sort_weight":131,"slug":133},10,"Lifestyle","lifestyle",{"id":135,"doc_module":4,"doc_module_name":45,"category_name":136,"show_sort_weight":105,"slug":137},19,"General","general"]