[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-seo-665450-105":3,"detail-sidebar-cat-0-en-105":80,"doc-detail-665450-en":130},{"code":4,"msg":5,"data":6},0,"ok",{"site_id":7,"language":8,"slug":9,"title":10,"keywords":11,"description":12,"schema_data":13,"social_meta":73,"head_meta":75,"extra_data":77,"updated_unix":79},105,"en","verification-of-arithmetic-circuits-with-binary-moment-diagrams","Verification of Arithmetic Circuits with Binary Moment Diagrams","","Binary Moment Diagrams (BMDs) provide a canonical symbolic representation for linear functions, analogous to how Binary Decision Diagrams represent Boolean functions. The approach embeds word-level data-path behavior by mapping Boolean-variable functions to integer results, efficiently capturing operations like integer multiplication. A hierarchical verification method first proves modules satisfy word-level specifications, then composes component functions and matches the composed result to a word-level circuit specification. Multipliers up to 256-bit words are verified using this technique.",{"@graph":14,"@context":72},[15,34,55],{"@type":16,"itemListElement":17},"BreadcrumbList",[18,23,27,31],{"item":19,"name":20,"@type":21,"position":22},"https://docshare.wps.com","Home","ListItem",1,{"item":24,"name":25,"@type":21,"position":26},"https://docshare.wps.com/document/","Document",2,{"item":28,"name":29,"@type":21,"position":30},"https://docshare.wps.com/document/research-report/","Research & Report",3,{"item":32,"name":10,"@type":21,"position":33},"https://docshare.wps.com/document/verification-of-arithmetic-circuits-with-binary-moment-diagrams/665450/",4,{"url":32,"name":10,"@type":35,"image":36,"author":41,"headline":10,"publisher":44,"fileFormat":47,"inLanguage":8,"description":12,"dateModified":48,"datePublished":49,"encodingFormat":47,"isAccessibleForFree":50,"interactionStatistic":51},"DigitalDocument",{"url":37,"@type":38,"width":39,"height":40},"https://docshare.wps.com/thumbnails/verification-of-arithmetic-circuits-with-binary-moment-diagrams/665450.png","ImageObject",300,407,{"name":42,"@type":43},"Genevieve","Person",{"url":19,"name":45,"@type":46},"DocShare","Organization","application/pdf","2026-10-30","2026-10-29",true,{"@type":52,"interactionType":53,"userInteractionCount":33},"InteractionCounter",{"@type":54},"ViewAction",{"@type":56,"mainEntity":57},"FAQPage",[58,64,68],{"name":59,"@type":60,"acceptedAnswer":61},"What are Binary Moment Diagrams (BMDs) used for?","Question",{"text":62,"@type":63},"BMDs represent linear functions over Boolean variables with numeric (integer) results. They are designed to model word-level behavior in data-path circuits more efficiently than bit-level representations.","Answer",{"name":65,"@type":60,"acceptedAnswer":66},"How does the proposed hierarchical verification work?",{"text":67,"@type":63},"First, each component module is verified to implement its word-level specification. Then the overall circuit functionality is verified by composing component functions and comparing the composed result to the word-level circuit specification.",{"name":69,"@type":60,"acceptedAnswer":70},"What circuit class and word sizes were verified using this technique?",{"text":71,"@type":63},"The technique verified multipliers with word sizes up to 256 bits, using the hierarchical composition of word-level representations.","https://schema.org",{"og:url":32,"og:type":74,"og:title":10,"og:site_name":45,"og:description":12},"article",{"robots":76,"canonical":32},"index,follow",{"doc_id":78,"site_id":7},665450,1793304255,{"code":4,"msg":81,"data":82},"success",[83,87,91,95,100,105,110,114,119,122,126],{"id":22,"doc_module":4,"doc_module_name":25,"category_name":84,"show_sort_weight":85,"slug":86},"Story & Novel",90,"story-novel",{"id":26,"doc_module":4,"doc_module_name":25,"category_name":88,"show_sort_weight":89,"slug":90},"Literature",80,"literature",{"id":33,"doc_module":4,"doc_module_name":25,"category_name":92,"show_sort_weight":93,"slug":94},"Exam",70,"exam",{"id":96,"doc_module":4,"doc_module_name":25,"category_name":97,"show_sort_weight":98,"slug":99},5,"Comic",60,"comic",{"id":101,"doc_module":4,"doc_module_name":25,"category_name":102,"show_sort_weight":103,"slug":104},6,"Technology",50,"technology",{"id":106,"doc_module":4,"doc_module_name":25,"category_name":107,"show_sort_weight":108,"slug":109},7,"Healthcare",40,"healthcare",{"id":111,"doc_module":4,"doc_module_name":25,"category_name":29,"show_sort_weight":112,"slug":113},8,30,"research-report",{"id":115,"doc_module":4,"doc_module_name":25,"category_name":116,"show_sort_weight":117,"slug":118},9,"Religion & Spirituality",20,"religion-spirituality",{"id":117,"doc_module":4,"doc_module_name":25,"category_name":120,"show_sort_weight":117,"slug":121},"World Cup","world-cup",{"id":123,"doc_module":4,"doc_module_name":25,"category_name":124,"show_sort_weight":123,"slug":125},10,"Lifestyle","lifestyle",{"id":127,"doc_module":4,"doc_module_name":25,"category_name":128,"show_sort_weight":96,"slug":129},19,"General","general",{"code":4,"msg":81,"data":131},{"doc_id":78,"user_id":132,"nickname":42,"user_avatar":133,"doc_module":4,"category_id":111,"category_name":29,"doc_title":10,"doc_description":12,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":33,"is_deleted":4,"is_public":22,"is_downloadable":22,"audit_status":22,"page_count":106,"language":139,"language_code":8,"site_id":7,"html_lang":8,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":12,"update_tm":79,"read_time":143},1374391974585,"https://ap-avatar.wpscdn.com/davatar_276721f389ce27ea32af1340a28f341c","Verification of Arithmetic Circuits with Binary Moment Diagrams􀀀  \nRandal E. Bryant, Yirng-An Chen Carnegie Mellon University Pittsburgh, PA 15213  \nAbstract—Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model the functionality of data path circuits operating over word-level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDshave simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs.  \nWe propose a hierarchical approach to verifying arithmetic circuits, where component modules are first shown to implement their word-level specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the word-level circuit specification. Multipliers with word sizes of up to 256 bits have been verified by this technique.  \n1. Introduction  \nBinary Decision Diagrams (BDDs) have proved successful for representing and manipulating Boolean functions symbolically [2] in a variety of application domains. Building on this success, there have been several efforts to extend the BDD concept to represent functions over Boolean variables, but having non-Boolean ranges, such as integers or real numbers [1, 5, 9] . Many tasks can be expressed in terms of operations on such functions, including integer linear programming, matrix manipulation, spectral transforms, and word-level digital system analysis. To date, the proposed representations for these functions have proved too fragile for routine application—too often the data structures grow exponentially in the number of variables.  \nIn this paper we propose a new representation called Multiplicative Binary Moment Diagrams (*BMDs) that improve on previous methods. *BMDs incorporate two novel features: they are based on a decomposition of a linear function in terms of its “moments,” and they have weights associated with their edges which are combined multiplicatively. These features have as heritage ideas found in previous function representations, namely the Reed-Muller decomposition used by Functional Decision Diagrams (FDDs) [8], and the additive edge  \n✁ This research is sponsoredby theWright Laboratory, AeronauticalSystems Center, Air Force Materiel Command, USAF, and the Advanced Research Projects Agency (ARPA) under grant number F33615-93-1-1330 .  \n0This paper will appear in the 32nd Design Automation Conference, June 1995.  \nFigure 1: Example Function Decompositions. MTBDDs are based on a pointwise decomposition (left), while BMDs are based on a linear decomposition (right) .  \nweights found in Edge-Valued Binary Decision Diagrams (EVBDDs)  \n[9] .  \n*BMDs are particularly effective for representing digital systems atthe word level, where sets of binary signals are interpreted as encoding integer values. Common integer encodings have efficient representations as *BMDs, as do operations such as addition and multiplication.  \n*BMDs can also represent Boolean functions as a special case, with size comparable to BDDs.  \n*BMDs can serve as the basis for a hierarchical methodology for verifying circuits such as multipliers. At the low level, we have a set of component modules such as add steppers, Booth steppers, and carry save adders described at both the bit level (in terms of logic gates) and at the word level (as algebraic expressions) . Using a methodology proposed by Lai and Vrudhula [9], we verify that the bit-level implementation of each block implements its word-level specification. Atthe higher level (or levels), a system is described as an interconnection of components having word-level representations, and the specification is als","cbCaitwIwruuGGKg","https://ap.wps.com/l/cbCaitwIwruuGGKg","pdf",158918,"English","# Introduction\n## The *BMD Data Structure\n### Function Decompositions","[{\"question\":\"What are Binary Moment Diagrams (BMDs) used for?\",\"answer\":\"BMDs represent linear functions over Boolean variables with numeric (integer) results. They are designed to model word-level behavior in data-path circuits more efficiently than bit-level representations.\"},{\"question\":\"How does the proposed hierarchical verification work?\",\"answer\":\"First, each component module is verified to implement its word-level specification. Then the overall circuit functionality is verified by composing component functions and comparing the composed result to the word-level circuit specification.\"},{\"question\":\"What circuit class and word sizes were verified using this technique?\",\"answer\":\"The technique verified multipliers with word sizes up to 256 bits, using the hierarchical composition of word-level representations.\"}]","Verification of Arithmetic Circuits with Binary Moment Diagrams | PDF",18]