[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-670853-105":59,"doc-detail-670853-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","ut81ndq512g8t-datasheet","UT81NDQ512G8T - Datasheet","","UT81NDQ512G8T NAND Flash datasheet details ONFI 4.0 and JEDEC interoperability compliance for a triple-level cell (TLC) device with B17A industrial die source. It specifies organization (x8 page size, block and plane structure) and multiple I/O modes including NV-DDR3, NV-DDR2, and asynchronous performance with clock and throughput figures. The document covers command sets, required external data randomization, reset and status detection, DQS signaling, copyback, ODT support, array performance, endurance, retention testing, operating voltage ranges, packaging, and radiation-qualified operational environment limits.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/ut81ndq512g8t-datasheet/670853/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/ut81ndq512g8t-datasheet/670853.png","ImageObject",300,407,{"name":92,"@type":93},"8796093062539","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-11-02","2026-11-01",true,{"@type":102,"interactionType":103,"userInteractionCount":8},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"Which standards does the UT81NDQ512G8T comply with?","Question",{"text":112,"@type":113},"It is described as compliant with ONFI 4.0 and JEDEC NAND Flash interoperability (JESD230C).","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"What data transfer interfaces and signaling are supported?",{"text":117,"@type":113},"The device supports asynchronous I/O as well as NV-DDR2 and NV-DDR3 high-performance interfaces. It uses a bidirectional data strobe (DQS) and related DQS signals for synchronization in the NV-DDR2/NV-DDR3 interface.",{"name":119,"@type":110,"acceptedAnswer":120},"What are the operating environment and reliability highlights?",{"text":121,"@type":113},"The operational temperature range is -40°C to +85°C, with total dose listed as 30 to 50 krad(Si) and SEL immune ≤ 60 MeV-cm2/mg. Reliability notes include JESD47-compliant data retention and endurance of 3,000 PROGRAM/ERASE cycles for TLC and 40,000 for SLC.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},670853,1793572047,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":66,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":133,"file_id":134,"file_url":135,"file_type":136,"file_size":137,"view_count":8,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":138,"language":139,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":67,"update_tm":129,"read_time":143},8796093062539,"DATASHEET  \nUT81NDQ512G8T  \n4Tb TLC NAND Flash  \n11/1/2022 Version \\#:1 .0.0  \nFeatures  \n• Open NAND Flash Interface (ONFI) 4.0-compliant1  \n• JEDEC NAND Flash Interoperability (JESD230C) compliant2  \n• Triple-level cell (TLC)  \n• B17A Industrial die source  \n• Organization  \n— Page size x8: 18,592 bytes (16,384 + 2208 bytes)  \n— Block size: 2304 pages, (36,864K + 4968K bytes)  \n— Plane size: 4 planes x 504 blocks  \n— Device size: 16128 blocks  \n• NV-DDR3 I/O performance3  \n— Up to NV-DDR3 timing mode 9  \n— Clock rate: 3ns (NV-DDR3)  \n— Read/write throughput per pin: 667 MT/s  \n—Tested over temperature in mode 9  \n• NV-DDR2 I/O performance4  \n— Up to NV-DDR2 timing mode 8  \n— Clock rate: 3.75ns (NV-DDR2)  \n— Read/write throughput per pin: 533 MT/s  \n—Tested over temperature in mode 6  \n• Asynchronous I/O performance4  \n— Up to asynchronous timing mode 5  \n—tRC/tWC: 20ns (MIN)  \n— Read/write throughput per pin: 50 MT/s  \n—Tested over temperature in mode 5  \n• TLC Array performance  \n— SNAP READ operation time without VPP: 51μs(TYP)  \n— Single-Plane READ PAGE operation time without/with VPP : 74/73μs (TYP)  \n— Multi-Plane READ PAGE operation time without VPP: 88μs(TYP)  \n— Effective Program page time without VPP: 1900μs(TYP)  \n— Erase block time: 15ms (TYP)  \n• Operating Voltage Range  \n—VCC: 2.7–3. 6V  \n—VCCQ: 1.14–1. 26V, 1.7–1.95V  \n• Command set: ONFI NAND Flash Protocol  \n• Data is required to be randomized by the external host prior to being inputted to the NAND device, see External Data Randomization in the User Manual  \n• First block (block address 00h) is valid when shipped from factory. For minimum required ECC, see Error Management in the User Manual5  \n• RESET (FFh) required as first command after power-on  \n• Operation status byte provides software method for detecting  \n— Operation completion  \n— Pass/fail condition  \n— Write-protect status  \n• Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the NVDDR2/NVDDR3 interface  \n• Copyback operations supported within the plane from which data is read  \n• On-die Termination (ODT)6  \n• Quality and reliability7  \n—Testing methodology: JESD47  \n— Data retention: JESD47 compliant  \n—TLC Endurance: 3,000 PROGRAM/ERASE cycles  \n— SLC Endurance: 40,000 PROGRAM/ERASE cycles  \n• Package  \n— 132-ball BGA  \n— ΘJC : 2.68 °C/W  \n— 2000V HBM ESD  \n— 0.534 grams  \nNotes:  \n1. The ONFI 4.0 specification is available [at](at www.onfi.org)[ ](at www.onfi.org)[www.onfi.org](at www.onfi.org)  \n2. The JEDEC specification is available [at](at www.jedec.org/standards-documents)[ ](at www.jedec.org/standards-documents)[www.jedec.org/standards-documents](at www.jedec.org/standards-documents)  \n3. NV-DDR3 functionality is only available with 1. 2V VCCQ  \n4. NV-DDR2 and Asynchronous functionality is only available with 1.8V VCCQ  \n5. ODT functionality is supported only in NV-DDR2 and NV-DDR3 mode  \n6. READ RETRY and AUTO READ CALIBRATION operations are required to achieve specified endurance and for general array data integrity  \n7. For minimum required ECC, see External Data Randomization in the User Manual  \n8. Radiation testing is performed without VPP. VPP operations should not be used in a radiation environment. Devices using VPP operations in a radiation environment will not be warrantied  \nOperational Environment  \n• Temperature Range: -40°C to +85°C  \n• Total Dose: 30 to 50 krad(Si)  \n• SEL Immune: ≤ 60 MeV-cm2/mg  \nNotes:  \n1. Radiation testing is performed without VPP. VPP operations should not be used in a radiation environment. Devices using VPP operations in a radiation environment will not be warrantied  \n2. Contact supplier for bit error performance and availability of material at a specific SLC and TLC TID levels  \nGeneral Description  \nNAND Flash devices include an asynchronous data interface for I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to imple","cbCaifwqNAXoROG2","https://ap.wps.com/l/cbCaifwqNAXoROG2","pdf",16536221,108,"English","# Features\n## Organization and I/O Performance\n## TLC Array Performance and Reliability\n## Operating Voltage and Command Set\n# General Description\n## Signal Interfaces and Definitions\n## Device and Array Concepts","[{\"question\":\"Which standards does the UT81NDQ512G8T comply with?\",\"answer\":\"It is described as compliant with ONFI 4.0 and JEDEC NAND Flash interoperability (JESD230C).\"},{\"question\":\"What data transfer interfaces and signaling are supported?\",\"answer\":\"The device supports asynchronous I/O as well as NV-DDR2 and NV-DDR3 high-performance interfaces. It uses a bidirectional data strobe (DQS) and related DQS signals for synchronization in the NV-DDR2/NV-DDR3 interface.\"},{\"question\":\"What are the operating environment and reliability highlights?\",\"answer\":\"The operational temperature range is -40°C to +85°C, with total dose listed as 30 to 50 krad(Si) and SEL immune ≤ 60 MeV-cm2/mg. Reliability notes include JESD47-compliant data retention and endurance of 3,000 PROGRAM/ERASE cycles for TLC and 40,000 for SLC.\"}]","UT81NDQ512G8T - Datasheet | PDF",272]