[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-665562-105":59,"doc-detail-665562-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","unit-2-circuit-design-process-nmoscmos-stick-diagrams-design-rules","Unit 2 - Circuit Design Process - NMOS/CMOS Stick Diagrams & Design Rules","","Unit 2 explains the circuit design process for MOS technologies with an emphasis on converting schematics into stick diagrams and mask/layout representations. It details the four basic fabrication layers and how insulating oxide separates them, then presents color/encoding conventions for NMOS, CMOS, and related structures. The chapter compares n- and p-transistor representation in CMOS style, discusses inverter and NAND/NOR stick-diagram construction, and covers dynamic shift-register layout concepts. It concludes with scalable λ-based design rules, including width, spacing, and gate overhang, and introduces vias as metal interconnects.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/unit-2-circuit-design-process-nmoscmos-stick-diagrams-design-rules/665562/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/unit-2-circuit-design-process-nmoscmos-stick-diagrams-design-rules/665562.png","ImageObject",300,407,{"name":92,"@type":93},"vwvw","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-30","2026-10-29",true,{"@type":102,"interactionType":103,"userInteractionCount":19},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What are the four basic layers used to form MOS circuits, and how are they separated?","Question",{"text":112,"@type":113},"MOS circuits are formed on N-diffusion, P-diffusion, polysilicon, and metal layers. These layers are isolated from each other by thick or thin silicon dioxide insulating layers.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"How are stick diagrams used to represent layer information for NMOS and CMOS?",{"text":117,"@type":113},"Stick diagrams convey layer information through encoding, such as using green for n-diffusion and red for poly. For CMOS, n-type and p-type diffusion are drawn in different colors (commonly green and brown), and transistor types are separated by a demarcation line in monochrome style.",{"name":119,"@type":110,"acceptedAnswer":120},"What design-rule parameter λ means in scalable Mead–Conway rules?",{"text":121,"@type":113},"Mead and Conway provide simplified scalable λ-based rules where the minimum feature size is characterized as 2λ. Width and spacing requirements are expressed in λ and then converted to actual dimensions based on the chosen technology scale.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},665562,1793304972,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":19,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":139,"language":140,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":141,"faqs":142,"seo_title":143,"seo_description":67,"update_tm":129,"read_time":144},3985747874149,"https://ap-avatar.wpscdn.com/avatar/3a001161165b4dc3d9e?x-image-process=image/resize,m_fixed,w_180,h_180&k=1790129441039064114","Unit 2  \nCircuit Design Process  \nIn this chapter we will be studying how to get the schematic into stick diagrams or layouts.  \nMOS circuits are formed on four basic layers:  \n􀀁 N-diffusion  \n􀀁 P-diffusion  \n􀀁 Polysilicon  \n􀀁 Metal  \nThese layers are isolated by one another by thick or thin silicon dioxide insulating layers.  \nThin oxide mask region includes n-diffusion / p-diffusion and transistor channel.  \nStick diagrams:  \nStick diagrams may be used to convey layer information through the use of a color code. For example: n-diffusion--green  \nEncodings for NMOS  \npoly blue yellow black  \nprocess:  \n--red  \n--metal  \n--implant  \n--contact areas  \nFigure 1: NMOS encodings  \nFigure shows the way of representing different layers in stick diagram notation and mask layout using nmos style.  \nFigure1 shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion mode transistor is represented in the stick format.  \nEncodings for CMOS process:  \nFigure 2: CMOS encodings  \nFigure 2 shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely.  \nFigure 2 also shows when a p-transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely.  \nEncoding for BJT and MOSFETs:  \nFigure 3: Bi CMOS encodings  \nThere are several layers in an nMOS chip:  \n_ a p-type substrate  \n_ paths of n-type diffusion  \n_ a thin layer of silicon dioxide  \n_ paths of polycrystalline silicon  \n_ a thick layer of silicon dioxide  \n_ paths of metal (usually aluminium)  \n_ a further thick layer of silicon dioxide  \nwith contact cuts through the silicon dioxide where connections are required.  \nThe three layers carrying paths can be considered as independent conductors that only interact  \nwhere polysilicon crosses diffusion to form a transistor. These tracks can be drawn as stick  \ndiagrams with  \n_ diffusion in green  \n_ polysilicon in red  \n_ metal in blue  \nusing black to indicate contacts between layers and yellow to mark regions of implant in the  \nchannels of depletion mode transistors.  \nWith CMOS there are two types of diffusion: n-type is drawn in green and p-type in brown.  \nThese are on the same layers in the chip and must not meet. In fact, the method of fabrication required that they be kept relatively far apart.  \nModern CMOS processes usually support more than one layer of metal. Two are common and three or more are often available.  \nActually, these conventions for colors are not universal; in particular, industrial (rather than academic) systems tend to use red for diffusion and green for polysilicon. Moreover, a shortage of colored pens normally means that both types of diffusion in CMOS are colored green and the polarity indicated by drawing a circle round p-type transistors or simply inferred from the context. Colorings for multiple layers of metal are even less standard.  \nThere are three ways that an nMOS inverter might be drawn:  \nFigure 4: nMOS depletion load inverter  \nFigure4 shows schematic, stick diagram and corresponding layout of nMOS depletion load inverter  \nFigure 5: CMOS inverter  \nFigure 5 shows the schematic, stick diagram and corresponding layout of CMOS inverter  \nFigure 6: nMOS depletion load NAND and NOR stick diagram  \nFigure6 shows the stick diagrams for nMOS NOR and NAND.  \nFigure 7: stick diagram of a given function f.  \nFigure 7 shows the stick diagram nMOS implementation of the function f=[(xy)+z]’  \nFigure 8: stick diagram of CMOS NAND and NOR  \nFigure 8 shows the stick diagram CMOS NOR and NAND, where we can see that the p diffusion line never touched the n diffusion directly, it is always joined using a blue color metal line.  \nNMOS and CMOS Design style:  \nIn the NMOS style of representing the sticks for the circuit, we use only NMOS transistor, in CMOS we need to differentiate n and p transist","cbCaidXkyyI3Ofew","https://ap.wps.com/l/cbCaidXkyyI3Ofew","pdf",2005732,11,"English","# Circuit Design Process\n## MOS Layers and Oxide Isolation\n## Stick Diagrams and Encodings (NMOS)\n## CMOS Encodings and Transistor Representation\n## nMOS Inverter, NAND/NOR, and Logic Functions\n## NMOS vs CMOS Design Style\n## Design Rules (Width, Spacing, Gate Overhang)\n## What is Via?","[{\"question\":\"What are the four basic layers used to form MOS circuits, and how are they separated?\",\"answer\":\"MOS circuits are formed on N-diffusion, P-diffusion, polysilicon, and metal layers. These layers are isolated from each other by thick or thin silicon dioxide insulating layers.\"},{\"question\":\"How are stick diagrams used to represent layer information for NMOS and CMOS?\",\"answer\":\"Stick diagrams convey layer information through encoding, such as using green for n-diffusion and red for poly. For CMOS, n-type and p-type diffusion are drawn in different colors (commonly green and brown), and transistor types are separated by a demarcation line in monochrome style.\"},{\"question\":\"What design-rule parameter λ means in scalable Mead–Conway rules?\",\"answer\":\"Mead and Conway provide simplified scalable λ-based rules where the minimum feature size is characterized as 2λ. Width and spacing requirements are expressed in λ and then converted to actual dimensions based on the chosen technology scale.\"}]","Unit 2 - Circuit Design Process - NMOS/CMOS Stick Diagrams & Design Rules | PDF",28]