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Covers the one-chip architecture combining P-channel MOS ROM, RAM, and arithmetic logic unit on a single semiconductor device. Explains how fixed ROM patterns are set via a single-level mask technique during wafer processing, and how the ROM program governs data input, storage, processing, and output behavior through the ALU and accumulator. Details key device organization, internal registers, I/O channel latches, PLA-based O decoding, R output storage elements, and the range of instruction capabilities for efficient operation.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/tms-1000-nc-tms-1200-nc-microcomputers-engineering-staff-datasheet/562978/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/tms-1000-nc-tms-1200-nc-microcomputers-engineering-staff-datasheet/562978.png","ImageObject",300,407,{"name":92,"@type":93},"pixelkiddo","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-13","2026-10-12",true,{"@type":102,"interactionType":103,"userInteractionCount":14},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What makes the TMS1000 series a one-chip microcomputer?","Question",{"text":112,"@type":113},"It integrates ROM, RAM, and an arithmetic logic unit on a single semiconductor chip, functioning as a single-chip binary computer.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"How is the ROM program specified for the TMS1000 series?",{"text":117,"@type":113},"Customer specifications determine the software reproduced during wafer processing using a single-level mask technique that defines a fixed ROM pattern.",{"name":119,"@type":110,"acceptedAnswer":120},"How do the O and R outputs work in the TMS1000 family?",{"text":121,"@type":113},"The O outputs are decoded from five data latches using a programmable logic array (PLA). The R outputs provide status/enable signals, strobe the O outputs to interfaces, and can multiplex data into the K inputs when needed.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},562978,1791906032,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":14,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":139,"language":140,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":141,"faqs":142,"seo_title":143,"seo_description":67,"update_tm":144,"read_time":145},962090883892,"https://ap-avatar.wpscdn.com/avatar/e00115db34f3e0f11b?x-image-process=image/resize,m_fixed,w_180,h_180&k=1790152879550218658","The Engineering Staff of  \nTEXAS INSTRUMENTS INCORPORATED  \nSemiconductor Group  \n# TMS 1000 SERIESMOS/LSI ONE-CHIPMICROCOMPUTERS\n\nTABLE OF CONTENTS  \n1. INTRODUCING A ONE-CHIP MICROCOMPUTER  \n1.1 Description ……………………………………………………………………………………………………………………………………………3  \n1.2 Applications ……………………………………………………………………………………………………………………………………………4  \n1.3 Design Support ………………………………………………………………………………………………………………………………………6  \n2. TMS1000-SERIES OPERATION  \n2.1 ROM Operation ………………………………………………………………………………………………………………………………………7  \n2.2 RAM Operation ………………………………………………………………………………………………………………………………………7  \n2.3 Arithmetic Logic Unit Operation ……………………………………………………………………………………………72.4 Input ……………………………………………………………………………………………………………………………………………………8  \n2.5 Output ……………………………………………………………………………………………………………………………………………………8  \n2.6 The Instruction Programmable Logic Array …………………………………………………………………………………9  \n2.7 Timing Relationships ……………………………………………………………………………………………………………………………9  \n2.8 Software Summary …………………………………………………………………………………………………………………………………9  \n2.9 Sample Program ………………………………………………………………………………………………………………………………………11  \n2.10 Power-On ………………………………………………………………………………………………………………………………………………12  \n3. ELECTRICAL AND MECHANICAL SPECIFICATIONS  \n3.1 Absolute Maximum Ratings ……………………………………………………………………………………………………………………14  \n3.2 Recommended Operating Conditions ……………………………………………………………………………………………………14  \n3.3 Electrical Characteristics ………………………………………………………………………………………………………………………14  \n3.4 Schematics of Inputs and Outputs …………………………………………………………………………………………………………15  \n3.5 Internal or External Clock …………………………………………………………………………………………………………………15  \n3.6 Terminal Assignments ……………………………………………………………………………………………………………………………16  \n3.7 Mechanical Data………………………………………………………………………………………………………………………………………16  \nLIST OF ILLUSTRATIONS  \nFigure 1...TMS1000-Series Logic Blocks………………………………………………………………………………………………3  \nFigure 2... Block Diagram of Typical Application-Terminal Controller ………………………:....5  \nFigure 3... TMS1000-Series Algorithm Development…………………………………………………………………………………6  \nFigure 4... ALU and Associated Data Paths………………………………………………………………………………………………7  \nFigure 5... Machine Instruction Flowchart-BCD-Addition Subroutine……………………………………………………13  \n1  \nInformation contained in this publication is believed to be accurateand reliable.However,responsibility is assumed neither for its usenor for any infringement of patents of rights of others that mayresult from its use.No license is granted by implication or otherwiseunder any patent or patent right ofTexas Instruments or others.  \nCopyright ◎ 1975Texas Instruments Incorporated  \n# TMS 1000 NC,TMS 1200 NC MICROCOMPUTERS\n\n## 1.  INTRODUCING A ONE-CHIP MICROCOMPUTER\n\n### 1.1 DESCRIPTION\n\nThe TMS1000 series is a family of P-channel MOS four-bit microcomputers with a ROM,a RAM,and an arithmeticlogic unit on a single semiconductor chip.The TMS1000 family is unique in the field of microprocessors because thisdevice is a single-chip binary computer.A customer's specification determines the software that is reproduced duringwafer processing by a single-level mask technique that defines a fixed ROM pattern.This versatile one-chip computer isvery cost effective and capable of performing a myriad of complex functions.  \nKey features of the TMS1000 series are:  \n\n| TMS1000 SERIES   |  |\n| --- | --- |\n| DEVICE   | PACKAGE   |\n| TMS1000NC  \u003Cbr>TMS1200NC   | 28-Pin DIP  \u003Cbr>40-Pin DIP   |\n\n● 8192-bit Read-Only Memory(ROM)on chip  \n● 256-bit Random-Access Memory(RAM)on chip  \n●Arithmetic Logic Unit(ALU)and 2 four-bit working registers on chip  \n● Conditional branching and subroutines  \n● Four-bit parallel data input  \n● 11 latched control/data-strobe outputs in a 28-pin package  \n● 13 latched control/data-strobe outputs in a 40-pin package  \n● 8 parallel data outputs and output programmable logic array(PLA)  \n● Programmable instruction decoder  \n● On-chip oscillator,or external synchronization if desired  \n● Singe-power-supply operation(15V)  \nR OUPUTS  \no0UTPU","cbCaibuvaQJTnqmr","https://ap.wps.com/l/cbCaibuvaQJTnqmr","pdf",1263249,17,"English","# 1. Introducing a One-Chip Microcomputer\n## 1.1 Description\n## 1.2 Applications\n## 1.3 Design Support\n# 2. TMS1000-Series Operation\n## 2.1 ROM Operation\n## 2.2 RAM Operation\n## 2.3 Arithmetic Logic Unit Operation\n## 2.4 Input\n## 2.5 Output\n## 2.6 The Instruction Programmable Logic Array\n## 2.7 Timing Relationships\n## 2.8 Software Summary\n## 2.9 Sample Program\n## 2.10 Power-On\n# 3. Electrical and Mechanical Specifications\n## 3.1 Absolute Maximum Ratings\n## 3.2 Recommended Operating Conditions\n## 3.3 Electrical Characteristics\n## 3.4 Schematics of Inputs and Outputs\n## 3.5 Internal or External Clock\n## 3.6 Terminal Assignments\n## 3.7 Mechanical Data","[{\"question\":\"What makes the TMS1000 series a one-chip microcomputer?\",\"answer\":\"It integrates ROM, RAM, and an arithmetic logic unit on a single semiconductor chip, functioning as a single-chip binary computer.\"},{\"question\":\"How is the ROM program specified for the TMS1000 series?\",\"answer\":\"Customer specifications determine the software reproduced during wafer processing using a single-level mask technique that defines a fixed ROM pattern.\"},{\"question\":\"How do the O and R outputs work in the TMS1000 family?\",\"answer\":\"The O outputs are decoded from five data latches using a programmable logic array (PLA). The R outputs provide status/enable signals, strobe the O outputs to interfaces, and can multiplex data into the K inputs when needed.\"}]","TMS 1000 NC, TMS 1200 NC Microcomputers - Engineering Staff Datasheet | PDF",1791810250,43]