[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-81986-en":3,"doc-seo-81986-105":30,"detail-sidebar-cat-0-en-105":92},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":13,"seo_description":14,"update_tm":28,"read_time":29},81986,1099514068035,"Ezra","https://ap-avatar.wpscdn.com/davatar_276721f389ce27ea32af1340a28f341c",8,"Research & Report","ThermoDSE Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators","Chiplet-based DNN accelerators offer a scalable route to balance performance and manufacturing yield, yet area and thermal constraints can severely limit viable designs. ThermoDSE targets this gap by building a thermal-aware, comprehensive design space exploration framework that jointly models fine-grained tasks, chiplet granularity, and core granularity while enforcing strict physical constraints. A unified simulation-and-optimization flow integrates architecture design, task orchestration, and inter-chiplet communication. Experiments show up to 3.5× improvement in an EnergyDelay-Inverse-Yield cost versus Simba and baselines, with large speedups over annealing and RL methods.","ThermoDSE: A Thermal-Aware and Comprehensive Design Space Exploration for Chiplet-Based DNN Accelerators  \nJian Peng, Student Member, IEEE, Hanwei Fan, Student Member, IEEE, Jingbo Jiang, Student Member, IEEE, Lin Jiang, Member, IEEE, Wei Zhang, Fellow, IEEE  \narXiv :2607 .07096v 1 [ cs .AR] 8 Jul 2026  \nAbstract—Chiplet-based DNN accelerators provide a scalable path to balance performance and yield for modern AI workloads. However, such systems face critical challenges in area and thermal constraints. The design space optimization should jointly consider the fine-grained task modeling, chiplet granularity, core granularity, and critical physical constraints. To the best of our knowledge, we are the first framework that involves all these factors. In this work, we propose ThermoDSE, a thermal-aware and comprehensive design space exploration framework for chiplet-based DNN accelerators. ThermoDSE integrates existing fine-grained modeling techniques into a uniform simulation and optimization framework that jointly considers architecture design, task orchestration, and inter-chiplet communication under strict thermal and area constraints. Experimental results show that ThermoDSE achieves up to 3.5× improvement in EnergyDelay-Inverse-Yield (defined as E × D × Y −1) cost, compared with state-of-the-art Simba and other baselines. Furthermore, relative to simulated annealing and reinforcement learning–based methods, ThermoDSE convert to better design points with 3.7× and 29.4× running time speed up, respectively.  \nIndex Terms—DNN accelerator, chiplet, thermal aware, task orchestration, optimization.  \nI. INTRODUCTION  \nCHIPLET technology has recently attracted significant  \nattention from both industry and academia due to the slowing of Moore’s Law. Smaller chiplets benefit from higher fabrication yields and shorter design cycles. By leveraging advanced packaging technologies, multiple chiplets can be integrated into a single package, delivering a flexible, highperformance processor at a reasonable cost. As computing demand for machine learning continues to increase, DNN accelerators are designed to meet stringent requirements, including high throughput, energy efficiency, and reliability. DNN accelerators featuring arrays of processing elements (PEs) have emerged as an efficient platform and have steadily grown in scale. For example, Cerebras [1] employs a wafer-scale accelerator to deliver cluster-scale throughput. However, such large monolithic dies result in significantly higher manufacturing cost. Moreover, due to their complexity, these accelerators face long development cycles and high non-recurring engineering (NRE) costs [2] .  \nManuscript received XXXX; revised XXXX; accepted XXXX. Data of publication XXXX; Date of current version XXXX. This work is partially funded by Hong Kong RGC GRF XXXX. Corresponding author: Wei Zhang. Jian Peng ([jpengai@connect.ust.hk](jpengai@connect.ust.hk)), Hanwei Fan ([hfanah@connect.ust.hk](hfanah@connect.ust.hk)),  \nJingbo Jiang ([jjiangan@connect.ust.hk](jjiangan@connect.ust.hk)), and Wei Zhang ([wei.zhang@ust.hk](wei.zhang@ust.hk))  \nare with the Dept. of Electronic and Computer Engineering, Hong Kong University of Science and Technology.  \nLin Jiang ([jianglin1@neu.edu.cn](jianglin1@neu.edu.cn)) is with Northeastern University, Shenyang, China.  \nChiplet-based DNN accelerators provide a promising solution to these problems. Simba [3], proposed by NVIDIA in 2019, is a 36-chiplet prototype for deep-learning inference. Each chiplet is an NVDLA-like NPU core that achieves a 4-TOPS peak performance within an area of only 2.5 mm × 2.4mm, leading to lower manufacturing and NRE costs. Several advantages arise from splitting a large monolithic DNN accelerator into smaller chiplets. First, smaller dies achieve much higher fabrication yield. Second, scalability improves since the number of chiplets can be easily extended with shorter development cycles.  \nFor chiplet-based DNN accelerators, core com","cbCaikLZ4IMz2ZJZ","https://ap.wps.com/l/cbCaikLZ4IMz2ZJZ","pdf",5698967,12,1,14,"English","en",105,"# Introduction\n## Chiplet technology and motivation\n## Background on Simba and chiplet-based accelerators\n## Communication and workload orchestration\n## Prior work limitations and thermal-wall challenges","[{\"question\":\"What problem does ThermoDSE address for chiplet-based DNN accelerators?\",\"answer\":\"ThermoDSE targets the need to optimize designs under both area and thermal constraints, where prior studies often miss one or more critical factors in chiplet and core granularity modeling.\"},{\"question\":\"What key factors does ThermoDSE jointly consider in its design space exploration?\",\"answer\":\"It jointly considers fine-grained task modeling, chiplet granularity, core granularity, and strict physical constraints, integrating architecture design, task orchestration, and inter-chiplet communication.\"},{\"question\":\"How does ThermoDSE improve results compared with existing methods?\",\"answer\":\"Experimental results report up to 3.5× improvement in EnergyDelay-Inverse-Yield cost versus Simba and other baselines, and up to 3.7× and 29.4× running-time speedups versus simulated annealing and reinforcement-learning–based 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problem does ThermoDSE address for chiplet-based DNN accelerators?","Question",{"text":76,"@type":77},"ThermoDSE targets the need to optimize designs under both area and thermal constraints, where prior studies often miss one or more critical factors in chiplet and core granularity modeling.","Answer",{"name":79,"@type":74,"acceptedAnswer":80},"What key factors does ThermoDSE jointly consider in its design space exploration?",{"text":81,"@type":77},"It jointly considers fine-grained task modeling, chiplet granularity, core granularity, and strict physical constraints, integrating architecture design, task orchestration, and inter-chiplet communication.",{"name":83,"@type":74,"acceptedAnswer":84},"How does ThermoDSE improve results compared with existing methods?",{"text":85,"@type":77},"Experimental results report up to 3.5× improvement in EnergyDelay-Inverse-Yield cost versus Simba and other baselines, and up to 3.7× and 29.4× running-time speedups versus simulated annealing and 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