[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-156010-105":59,"doc-detail-156010-en":131},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":124,"head_meta":126,"extra_data":128,"updated_unix":130},105,"en","the-potential-of-programmable-logic-in-the-middle-cache-bleaching","The Potential of Programmable Logic in the Middle - Cache Bleaching","","Consolidating hard real-time systems onto modern multi-core Systems-on-Chip raises unpredictability because shared memory hierarchy resources are uncontrollably contested across applications. The issue intensifies when Cyber-Physical Systems expect real-time workload guarantees on increasingly complex heterogeneous platforms. The work proposes Programmable Logic In-the-Middle (PLIM) by inserting programmable logic between multi-core processors and main memory to manipulate individual memory transactions. It delivers Cache Bleaching to prevent fragmentation and enable zero-copy re-coloring, supported by a proof-of-concept implementation and real-application evaluation, plus hypervisor-level adaptations.",{"@graph":69,"@context":123},[70,84,106],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":40,"@type":76,"position":81},"https://docshare.wps.com/document/research-report/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/the-potential-of-programmable-logic-in-the-middle-cache-bleaching/156010/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/the-potential-of-programmable-logic-in-the-middle-cache-bleaching/156010.png","ImageObject",300,407,{"name":92,"@type":93},"Genevieve","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-29","2026-08-28",true,{"@type":102,"interactionType":103,"userInteractionCount":105},"InteractionCounter",{"@type":104},"ViewAction",13,{"@type":107,"mainEntity":108},"FAQPage",[109,115,119],{"name":110,"@type":111,"acceptedAnswer":112},"What problem does the paper address in multi-core SoCs for real-time systems?","Question",{"text":113,"@type":114},"It addresses unpredictability caused by lack of fine-grained control over shared hardware components in the memory hierarchy, leading to temporal coupling between applications when real-time guarantees are required.","Answer",{"name":116,"@type":111,"acceptedAnswer":117},"What is Programmable Logic In-the-Middle (PLIM)?",{"text":118,"@type":114},"PLIM inserts programmable logic between a traditional multi-core processor and main memory so the system can manipulate individual memory transactions, enabling new resource-management capabilities beyond OS-only or hardware-redesign alternatives.",{"name":120,"@type":111,"acceptedAnswer":121},"How does PLIM help with cache coloring and Cache Bleaching?",{"text":122,"@type":114},"By enabling control over memory transactions, PLIM lifts limitations of traditional page coloring, preventing address fragmentation in main memory and supporting compaction plus zero-copy re-coloring of live applications or virtual machines.","https://schema.org",{"og:url":83,"og:type":125,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":127,"canonical":83},"index,follow",{"doc_id":129,"site_id":62},156010,1787942650,{"code":4,"msg":5,"data":132},{"doc_id":129,"user_id":133,"nickname":92,"user_avatar":134,"doc_module":4,"category_id":39,"category_name":40,"doc_title":65,"doc_description":67,"doc_content":135,"file_id":136,"file_url":137,"file_type":138,"file_size":139,"view_count":105,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":140,"language":141,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":142,"faqs":143,"seo_title":144,"seo_description":67,"update_tm":130,"read_time":145,"preview_page_count":4},1374391974585,"https://ap-avatar.wpscdn.com/davatar_276721f389ce27ea32af1340a28f341c","The Potential of Programmable Logic in the Middle: Cache Bleaching  \nShahin Roozkhosh  \nBoston University, USA [shahin@bu.edu](shahin@bu.edu)  \nRenato Mancuso  \nBoston University, USA[rmancuso@bu.edu](rmancuso@bu.edu)  \nAbstract—Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in nextgeneration Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.  \nStrong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.  \nI. INTRODUCTION  \nThe modern world and society is supported by safety-critical Cyber-Physical Systems (CPS) with strict reliability and confidentiality requirements: avionic systems, nuclear plant supervisory systems, orbit controllers in satellites, space station life support apparatuses, unmanned aerial vehicles (UAVs) flight controllers, surgeon-machine interfaces in robotic surgery devices, and driverless cars, to name a few. In the last decade, we have entered a new era where bold new expectations are set on the capabilities of a CPS. Following the push for smarter CPS's, embedded platforms have substantially increased in complexity. Multi-core heterogeneous embedded systems have become mainstream for high-performance CPS's. But complexity comes at the cost of a fundamental lack of predictability. As a single backbone of memory resources is shared by multiple processors, the unmanaged contention introduces non-negligible temporal coupling between logically unrelated applications on the same SoC. The design of (1) new multi-core hardware platforms, and of (2) OS-level techniques to regulate contention have been the two main directions followed by this community to achieve performance isolation. In this work, we outline a third possible direction. We consider modern, commercially available SoCs that include  \nprogrammable logic (PL) and a traditional multi-core processor on the same chip. With this, we show that it is possible to instantiate logic that acts as an intermediary between embedded processors and main memory. By sitting between CPUsand main memory, we achieve a new degree of control over memory transactions. We call this approach Programmable Logic In-the-Middle (PLIM) . The PLIM approach opens up new avenues to design and deploy resource management primitives previously available only though hardware re-design. It also creates new opportunities in the definition of OS-level and hypervisor-level technologies that leverage PLIM modules to improve performance management, self-awareness, and online workload characterization.  \nIn the rest of this paper, we first lay the fundamental principles for the definition of PLIM modules. Then, we demonstrate that PLIM can be used to re-think known management primitives and solve some of their long-standing shortcomings. More sp","cbCaibKThU4J7CHj","https://ap.wps.com/l/cbCaibKThU4J7CHj","pdf",952878,14,"English","# Introduction\n## PLIM overview and principles\n## Cache partitioning via page coloring\n# Overview\n## The PLIM approach on commercial platforms\n## Hardware modules and hypervisor adaptations","[{\"question\":\"What problem does the paper address in multi-core SoCs for real-time systems?\",\"answer\":\"It addresses unpredictability caused by lack of fine-grained control over shared hardware components in the memory hierarchy, leading to temporal coupling between applications when real-time guarantees are required.\"},{\"question\":\"What is Programmable Logic In-the-Middle (PLIM)?\",\"answer\":\"PLIM inserts programmable logic between a traditional multi-core processor and main memory so the system can manipulate individual memory transactions, enabling new resource-management capabilities beyond OS-only or hardware-redesign alternatives.\"},{\"question\":\"How does PLIM help with cache coloring and Cache Bleaching?\",\"answer\":\"By enabling control over memory transactions, PLIM lifts limitations of traditional page coloring, preventing address fragmentation in main memory and supporting compaction plus zero-copy re-coloring of live applications or virtual machines.\"}]","The Potential of Programmable Logic in the Middle - Cache Bleaching | PDF",35]