[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-124188-en":3,"doc-seo-124188-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},124188,1374391975076,"Riley","https://ap-avatar.wpscdn.com/avatar/14000253ca4ec9f6853?x-image-process=image/resize,m_fixed,w_180,h_180&k=1783305029341752051",8,"Research & Report","The Hyper-Dimensional Processing Unit - Energy-Efficient Machine Learning Using Vector-Symbolic Architectures","Hyper-dimensional computing (HDC) is leveraged as a low-power machine learning framework for edge-AI tasks, especially biosensing classification, where bitwise vector operations and limited memory improve energy efficiency over conventional approaches. Growing HDC system interest has introduced algorithms enabling cognitive reasoning and control, but prior hardware struggles as application demands broaden. This dissertation presents the goals, design, optimization, and implementation of an energy-efficient multipurpose processor for HDC, the Hyper-Dimensional Processing Unit (HPU). The work includes analysis of earlier hardware, two HPU tape-outs, and evaluation showing HPUv2 reaches 168 pJ per operation, supporting edge intelligent HDC systems.","UC Berkeley  \nUC Berkeley Electronic Theses and Dissertations  \nTitle  \nThe Hyper-Dimensional Processing Unit: Energy-Efficient Machine Learning Using VectorSymbolic Architectures  \nPermalink  \n[https://escholarship.org/uc/item/2119r02v](https://escholarship.org/uc/item/2119r02v)  \nAuthor  \nKim, Youbin  \nPublication Date  \n2024  \nPeer reviewed|Thesis/dissertation  \n[eScholarship.org](eScholarship.org) Powered by the California Digital Library  \nUniversity of California  \nThe Hyper-Dimensional Processing Unit: Energy-Efficient Machine Learning Using  \nVector-Symbolic Architectures  \nBy  \nYoubin Kim  \nA dissertation submitted in partial satisfaction of the requirements for the degree of  \nDoctor of Philosophy  \nin  \nEngineering – Electrical Engineering and Computer Science  \nin the  \nGraduate Division  \nof the  \nUniversity of California, Berkeley  \nCommittee in charge:  \nProfessor Jan M. Rabaey, Chair  \nProfessor Bruno Olshausen  \nProfessor Sayeef Salahuddin  \nFall 2024  \nThe Hyper-Dimensional Processing Unit: Energy-Efficient Machine Learning Using  \nVector-Symbolic Architectures  \nCopyright 2024  \nby  \nYoubin Kim  \n1  \nAbstract  \nThe Hyper-Dimensional Processing Unit: Energy-Efficient Machine Learning Using  \nVector-Symbolic Architectures  \nby  \nYoubin Kim  \nDoctor of Philosophy in Engineering – Electrical Engineering and Computer Science  \nUniversity of California, Berkeley  \nProfessor Jan M. Rabaey, Chair  \nHyper-Dimensional computing (HDC) is a machine learning framework that has made inroads in low-power edge-AI applications. With simple bitwise vector operations and a small memory footprint, HDC demonstrates improved energy-efficiency for biosensing classification tasks compared to conventional machine learning methods. Recent interest in HDC has developed complex algorithms that enable the use of HDC systems for cognitive reasoning and control applications. Although previous hardware for HDC achieve impressive energyefficiency for certain tasks, they face several issues with the growing application space. This dissertation covers the goals, design, optimization, and implementation of an energy-efficient multipurpose processor for HDC.  \nThe first half of the dissertation overviews the recent expansion of HDC algorithms and the corresponding hardware to implement them efficiently. The shortcomings of previous hardware for HDC is analyzed and used to create goals for the Hyper-Dimensional Processing Unit (HPU), the first multipurpose HDC processor. The second half describes the physical realization and optimization of the HPU, characterized with two tape-outs. HPUv2 achievesan impressive energy-efficiency of 168pJ per operation, making it competitive with previous application-specific hardware. The fabrication, verification, and characterization of the HPU architecture demonstrate the viability of an energy-efficient multipurpose processor that can enable intelligent HDC systems on the edge.  \ni  \nContents  \nContents i  \nList of Figures iii  \nList of Tables vi  \n1 Introduction 1  \n1.1 Energy-Efficient Machine Learning ....................... 1  \n1.2 Hyper-Dimensional Computing ......................... 3  \n1.3 Encoding and Computing with HD Vectors ................... 6  \n1.4 Applications of HDC ............................... 9  \n1.5 Custom Hardware for Energy-Efficient HDC .................. 11  \n1.6 Outline ....................................... 12  \n2 Investigating Non-Classification HDC Algorithms 13  \n2.1 HD Factorization ................................. 13  \n2.2 Recall of Reactive Behavior ........................... 17  \n2.3 Conclusion ..................................... 20  \n3 The Design of the Hyper-Dimensional Processing Unit (HPU) 22  \n3.1 Introduction .................................... 22  \n3.2 Previous ASICs for HDC ............................. 22  \n3.3 Goals of the HPU ................................. 23  \n3.4 HPU System Architecture ............................ 25  \n3.5 Dimensionality Scaling ......","cbCaivucdGuuRxoG","https://ap.wps.com/l/cbCaivucdGuuRxoG","pdf",45186365,1,100,"English","en",105,"# Introduction\n## Energy-Efficient Machine Learning\n## Hyper-Dimensional Computing\n## Encoding and Computing with HD Vectors\n## Applications of HDC\n## Custom Hardware for Energy-Efficient HDC\n## Outline\n# Investigating Non-Classification HDC Algorithms\n## HD Factorization\n## Recall of Reactive Behavior\n## Conclusion\n# The Design of the Hyper-Dimensional Processing Unit (HPU)\n## Previous ASICs for HDC\n## Goals of the HPU\n## HPU System Architecture\n## Dimensionality Scaling\n## Pseudo-Random Generation using Cellular Automata\n## Conclusion\n# HPUv1: Design and Implementation\n## Processor Design\n## Physical Implementation\n## Chip Verification and Measurement\n## Power and Performance Bottlenecks\n# HPUv2: Optimization and Characterization\n## Energy Optimization and Updates\n## Physical Implementation\n## Chip Measurements\n## Discussion\n# Conclusions\n## Summary of Results\n## Future Work\n## Looking Forward","[{\"question\":\"What problem does the dissertation address?\",\"answer\":\"It addresses the challenge of scaling HDC hardware to a growing application space while maintaining energy efficiency and supporting complex HDC algorithms.\"},{\"question\":\"What is HPUv2 and what performance does it achieve?\",\"answer\":\"HPUv2 is a realization of the Hyper-Dimensional Processing Unit, optimized through energy-focused design choices. It achieves an energy efficiency of 168 pJ per operation in the reported measurements.\"},{\"question\":\"How is the dissertation structured across HDC algorithms and hardware?\",\"answer\":\"The first half reviews HDC algorithm expansion and existing hardware, analyzes shortcomings, and sets design goals for the first multipurpose HDC processor (HPU). The second half describes physical implementation and optimization, including two tape-outs and system characterization.\"}]","The Hyper-Dimensional Processing Unit - Energy-Efficient Machine Learning Using Vector-Symbolic Architectures | PDF",1785820936,252,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":28},"the-hyper-dimensional-processing-unit-energy-efficient-machine-learning-using-vector-symbolic-architectures","",{"@graph":36,"@context":85},[37,54,68],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/research-report/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/the-hyper-dimensional-processing-unit-energy-efficient-machine-learning-using-vector-symbolic-architectures/124188/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":62,"encodingFormat":61,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-08-04",true,{"@type":65,"interactionType":66,"userInteractionCount":4},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"What problem does the dissertation address?","Question",{"text":75,"@type":76},"It addresses the challenge of scaling HDC hardware to a growing application space while maintaining energy efficiency and supporting complex HDC algorithms.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"What is HPUv2 and what performance does it achieve?",{"text":80,"@type":76},"HPUv2 is a realization of the Hyper-Dimensional Processing Unit, optimized through energy-focused design choices. It achieves an energy efficiency of 168 pJ per operation in the reported measurements.",{"name":82,"@type":73,"acceptedAnswer":83},"How is the dissertation structured across HDC algorithms and hardware?",{"text":84,"@type":76},"The first half reviews HDC algorithm expansion and existing hardware, analyzes shortcomings, and sets design goals for the first multipurpose HDC processor (HPU). The second half describes physical implementation and optimization, including two tape-outs and system characterization.","https://schema.org",{"og:url":52,"og:type":87,"og:title":13,"og:site_name":59,"og:description":14},"article",{"robots":89,"canonical":52},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":92},[93,97,101,105,110,115,120,123,128,131,135],{"id":20,"doc_module":4,"doc_module_name":46,"category_name":94,"show_sort_weight":95,"slug":96},"Story & Novel",90,"story-novel",{"id":47,"doc_module":4,"doc_module_name":46,"category_name":98,"show_sort_weight":99,"slug":100},"Literature",80,"literature",{"id":53,"doc_module":4,"doc_module_name":46,"category_name":102,"show_sort_weight":103,"slug":104},"Exam",70,"exam",{"id":106,"doc_module":4,"doc_module_name":46,"category_name":107,"show_sort_weight":108,"slug":109},5,"Comic",60,"comic",{"id":111,"doc_module":4,"doc_module_name":46,"category_name":112,"show_sort_weight":113,"slug":114},6,"Technology",50,"technology",{"id":116,"doc_module":4,"doc_module_name":46,"category_name":117,"show_sort_weight":118,"slug":119},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":121,"slug":122},30,"research-report",{"id":124,"doc_module":4,"doc_module_name":46,"category_name":125,"show_sort_weight":126,"slug":127},9,"Religion & Spirituality",20,"religion-spirituality",{"id":126,"doc_module":4,"doc_module_name":46,"category_name":129,"show_sort_weight":126,"slug":130},"World Cup","world-cup",{"id":132,"doc_module":4,"doc_module_name":46,"category_name":133,"show_sort_weight":132,"slug":134},10,"Lifestyle","lifestyle",{"id":136,"doc_module":4,"doc_module_name":46,"category_name":137,"show_sort_weight":106,"slug":138},19,"General","general"]