[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-151504-en":3,"doc-seo-151504-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},151504,3985741905716,"Kyle","https://ap-avatar.wpscdn.com/davatar_994ba38a5ba835b3df7d355c54d3ed8d",6,"Technology","Standard Gotchas in Verilog and SystemVerilog - Part 1 - Subtleties","“Gotcha” refers to language misfeatures that invite easy use yet produce surprising or unreasonable outcomes, breeding bugs through misunderstandings. This paper explains how the Verilog and SystemVerilog standards specify hundreds of subtle interpretation rules for tools handling design and testbench code. It reveals key gotchas with practical guidance for avoiding them, drawing from multiple sections such as declaration issues, two-state behavior, literal number pitfalls, and operator semantics.","Standard Gotchas  \nSubtleties in the Verilog and SystemVerilog Standards That  \nEvery Engineer Should Know  \nStuart Sutherland  \nSutherland HDL, Inc.  \n[stuart@sutherland-hdl.com](stuart@sutherland-hdl.com)  \nDon Mills  \nMicrochip Technology  \n[don.mills@microchip.com](don.mills@microchip.com)  \nABSTRACT  \nA definition of “gotcha” is: “A misfeature of....a programming language...that tends to breed bugs or mistakes because it is both enticingly easy to invoke and completely unexpected and/or unreasonable in its outcome. A classic gotcha in C is the fact that ‘if (a=b) {code;}’ is syntactically valid and sometimes even correct. It puts the value of b into a and then executes code if a is non-zero. What the programmer probably meant was ‘if (a==b) {code;} ’, which executes code if a and b are equal.”(from [http://www.hyperdictionary.com/computing/gotcha](http://www.hyperdictionary.com/computing/gotcha))  \nThe Verilog and SystemVerilog standards define hundreds of subtle rules on how software tools should interpret design and testbench code. These subtle rules are documented in the IEEE Verilog and SystemVerilog Language Reference Manuals...all 1,500 plus pages! The goal of this paper is to reveal many of the mysteries of Verilog and SystemVerilog, and help engineers understand many of the important underlying rules of the Verilog and SystemVerilog languages. Dozens of gotchas in the standards are explained, along with tips on how to avoid these gotchas.  \nTable of Contents  \n1.0 Introduction ............................................................................................................................3  \n2.0 Declaration gotchas ................................................................................................................4  \n2.1 Case sensitivity ............................................................................................................ 4  \n2.2 Implicit net declarations ............................................................................................... 5  \n2.3 Escaped identifiers in hierarchy paths ......................................................................... 6  \n2.4 Verification of dynamic data ....................................................................................... 7  \n2.5 Variables declared in unnamed blocks ........................................................................ 8  \n2.6 Hierarchical references to declarations imported from packages ................................ 8  \n2.7 Variables with no hierarchy path are not dumped to VCD files .................................. 9  \n2.8 Shared variables in modules ........................................................................................ 9  \nSNUG Boston 2006 1 Standard Gotchas in Verilog and SystemVerilog  \n2.9 Shared variables in interfaces, packages, and $unit ................................................... 10  \n2.10 Shared variables in tasks and functions ..................................................................... 10  \n2.11 Importing enumerated types from packages .............................................................. 11  \n2.12 Importing from multiple packages ............................................................................. 11  \n3.0 Two-state gotchas ................................................................................................................ 12  \n3.1 Resetting 2-state models ............................................................................................ 12  \n3.2 Locked state machines ............................................................................................... 13  \n3.3 Hidden design problems ............................................................................................ 15  \n3.4 Out-of-bounds indication lost .................................................................................... 16  \n4.0 Literal number gotchas ...................................................","cbCaivD7YHsZt185","https://ap.wps.com/l/cbCaivD7YHsZt185","pdf",405843,1,63,"English","en",105,"# Introduction\n# Declaration gotchas\n## Case sensitivity\n## Implicit net declarations\n## Escaped identifiers in hierarchy paths\n## Verification of dynamic data\n## Variables declared in unnamed blocks\n## Hierarchical references to declarations imported from packages\n## Variables with no hierarchy path are not dumped to VCD files\n## Shared variables in modules\n## Shared variables in interfaces, packages, and $unit\n## Shared variables in tasks and functions\n## Importing enumerated types from packages\n## Importing from multiple packages\n# Two-state gotchas\n## Resetting 2-state models\n## Locked state machines\n## Hidden design problems\n## Out-of-bounds indication lost\n# Literal number gotchas\n## Signed versus unsigned literal integers\n## Default base of literal integers\n## Size mismatch in literal integers\n## Literal number size mismatch in assignments\n## Literal number Z and X extension backward compatibility\n## Filling vectors\n## Passing real (floating point) numbers through ports\n## Port connection rules\n## Back-driven input ports\n# Operator gotchas\n## Self-determined operations versus context-determined operations\n## Operation size and sign extension in assignment statements\n## Signed arithmetic\n## Bit select and part select operations\n## Increment, decrement and assignment operations\n## Pre-increment versus post-increment operations","[{\"question\":\"What does “gotcha” mean in the context of programming languages?\",\"answer\":\"A “gotcha” is a language misfeature that is enticingly easy to invoke but yields unexpected or unreasonable results, which can lead to bugs through incorrect assumptions.\"},{\"question\":\"Why do Verilog and SystemVerilog standards contain many “gotchas”?\",\"answer\":\"The standards define hundreds of subtle rules describing how tools should interpret design and testbench code, and these details can be easily misunderstood or missed.\"},{\"question\":\"What kinds of gotchas does the paper explain?\",\"answer\":\"It covers gotchas across multiple areas, including declaration rules, two-state model behavior, literal number handling, and operator semantics, along with tips to avoid common pitfalls.\"}]","Standard Gotchas in Verilog and SystemVerilog - Part 1 - Subtleties | PDF",1787841792,159,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":28},"standard-gotchas-in-verilog-and-systemverilog-part-1-subtleties","",{"@graph":36,"@context":85},[37,54,68],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/technology/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/standard-gotchas-in-verilog-and-systemverilog-part-1-subtleties/151504/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":62,"encodingFormat":61,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-08-27",true,{"@type":65,"interactionType":66,"userInteractionCount":4},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"What does “gotcha” mean in the context of programming languages?","Question",{"text":75,"@type":76},"A “gotcha” is a language misfeature that is enticingly easy to invoke but yields unexpected or unreasonable results, which can lead to bugs through incorrect assumptions.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"Why do Verilog and SystemVerilog standards contain many “gotchas”?",{"text":80,"@type":76},"The standards define hundreds of subtle rules describing how tools should interpret design and testbench code, and these details can be easily misunderstood or missed.",{"name":82,"@type":73,"acceptedAnswer":83},"What kinds of gotchas does the paper explain?",{"text":84,"@type":76},"It covers gotchas across multiple areas, including declaration rules, two-state model behavior, literal number handling, and operator semantics, along with tips to avoid common pitfalls.","https://schema.org",{"og:url":52,"og:type":87,"og:title":13,"og:site_name":59,"og:description":14},"article",{"robots":89,"canonical":52},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":92},[93,97,101,105,110,113,118,123,128,131,135],{"id":20,"doc_module":4,"doc_module_name":46,"category_name":94,"show_sort_weight":95,"slug":96},"Story & Novel",90,"story-novel",{"id":47,"doc_module":4,"doc_module_name":46,"category_name":98,"show_sort_weight":99,"slug":100},"Literature",80,"literature",{"id":53,"doc_module":4,"doc_module_name":46,"category_name":102,"show_sort_weight":103,"slug":104},"Exam",70,"exam",{"id":106,"doc_module":4,"doc_module_name":46,"category_name":107,"show_sort_weight":108,"slug":109},5,"Comic",60,"comic",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":111,"slug":112},50,"technology",{"id":114,"doc_module":4,"doc_module_name":46,"category_name":115,"show_sort_weight":116,"slug":117},7,"Healthcare",40,"healthcare",{"id":119,"doc_module":4,"doc_module_name":46,"category_name":120,"show_sort_weight":121,"slug":122},8,"Research & Report",30,"research-report",{"id":124,"doc_module":4,"doc_module_name":46,"category_name":125,"show_sort_weight":126,"slug":127},9,"Religion & Spirituality",20,"religion-spirituality",{"id":126,"doc_module":4,"doc_module_name":46,"category_name":129,"show_sort_weight":126,"slug":130},"World Cup","world-cup",{"id":132,"doc_module":4,"doc_module_name":46,"category_name":133,"show_sort_weight":132,"slug":134},10,"Lifestyle","lifestyle",{"id":136,"doc_module":4,"doc_module_name":46,"category_name":137,"show_sort_weight":106,"slug":138},19,"General","general"]