[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-83195-en":3,"doc-seo-83195-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":13,"seo_description":14,"update_tm":28,"read_time":29},83195,1374391974468,"Eden","https://ap-avatar.wpscdn.com/davatar_29158cc5080c5b710cf443261637dec0",8,"Research & Report","Separation Logic for Memory Conflict Detection in High-Level Synthesis","High-Level Synthesis relies on loop unrolling and array partitioning, yet parallel scheduling becomes difficult when index expressions include non-affine arithmetic. Conventional polyhedral methods over-approximate such transformations, enforcing conservative serialization that reduces performance. A spatial verification framework operates at the LLVM IR level, extracting flat address arithmetic from getelementptr and modeling memory banks as polymorphic spatial predicates. Conflict-Free Unrolling is enforced via Separation Logic with SMT-based pairwise inequalities and a deterministic sequential fallback for undecidable cases, with a soundness theorem connecting SMT checks to RTL trace safety.","arXiv :2607 .07 126v 1 [ cs .LO] 8 Jul 2026  \nSEPARATION LOGIC FOR MEMORY CONFLICT DETECTION IN  \nHIGH-LEVEL SYNTHESIS  \nYeonseok Lee  \nSLING AI Inc.  \nIncheon, Republic of Korea  \n[ylee@sling.ai.kr](ylee@sling.ai.kr)  \nABSTRACT  \nHigh-Level Synthesis leverages loop unrolling and array partitioning, but scheduling concurrent accesses is challenging when indices contain non-affine arithmetic. Conventional polyhedral frameworks systematically over-approximate these non-linear transformations, forcing conservative serialization that degrades performance. To minimize this bottleneck, we present a spatial verification framework operating at the LLVM Intermediate Representation (IR) level. By extracting flat arithmetic expressions from “getelementptr” instructions, it models memory banks as polymorphic spatial predicates to handle non-affine terms. Structural safety is enforced via a Conflict-Free Unrolling condition using Separation Logic’s separating conjunction; concurrent operations targeting the same bank trigger an automatic spatial contradiction. This disjointness requirement is reduced to a matrix of pairwise inequalities over immutable Static Single Assignment (SSA) variables for a Satisfiability Modulo Theories (SMT) oracle. To guarantee safety against undecidable non-linear arithmetic, we implement a deterministic sequential fallback. Finally, a theorem of soundness bridges algebraic SMT verification with Register Transfer Level trace safety, ensuring physical hardware immune to structural memory collisions.  \nKeywords High-Level Synthesis · Separation Logic · LLVM IR · Memory Conflict Detection · SMT  \n1 Introduction  \n1.1 The Drive for Hardware Parallelism in HLS  \nHigh-Level Synthesis (HLS) drastically shortens the hardware development cycle by shifting design entry from structural Register Transfer Level (RTL) syntax up to high-level programming languages like C/C++ [1, 2] . Modern state-ofthe-art HLS frameworks leverage compiler optimization pipelines to extract loop-level parallelism and automatically schedule operations into efficient parallel hardware architectures [3, 4] . To fully match this computational parallelism, the underlying memory system must deliver high bandwidth, which FPGAs achieve by partitioning and distributing application data across multiple isolated on-chip memory blocks or banks [5] . Loop unrolling duplicates sequential basic blocks to expose concurrent iteration traces within a single clock cycle, but its throughput gains are fundamentally bounded by the memory infrastructure’s ability to support non-interfering parallel data accesses [6] .  \n1.2 The Bottleneck: Memory Conflicts and Affine Limitations  \nConcurrently scheduling these duplicated memory instructions incurs a significant risk of structural hazards when multiple parallel operations attempt to access the same single-ported memory bank during the same clock cycle. To track array coordinates within multi-dimensional iteration spaces, standard dependency solvers historically employ the polyhedral model [7] . However, these geometric techniques are bounded to static control structures where loop boundsand array access functions are affine combinations of enclosing loop variables.  \nIn the presence of pointer arithmetic, dynamic memory allocation, or non-affine index strings—such as symbolic register multiplication, division, or modulo arithmetic—conventional analyses encounter limitations. Because legacy  \nSeparation Logic for Memory Conflict Detection in High-Level Synthesis  \nframeworks over-approximate systematically at the first sign of non-linear transformations, they trigger a safe but conservative fallback. This forces them to assume a dependency between all memory statements, resulting in a monolithic heap allocation that destroys potential parallelism. While conservative serialization remains a critical mathematical necessity to guarantee absolute safety when non-linear integer arithmetic cannot be resolved, executing this f","cbCaijcMVgq4OqGb","https://ap.wps.com/l/cbCaijcMVgq4OqGb","pdf",420430,2,1,14,"English","en",105,"# Introduction\n## The Drive for Hardware Parallelism in HLS\n## The Bottleneck: Memory Conflicts and Affine Limitations\n## A Spatial Resolution: Separation Logic\n## Contributions","[{\"question\":\"Why do conventional polyhedral frameworks struggle with non-affine index arithmetic in HLS scheduling?\",\"answer\":\"They systematically over-approximate non-linear transformations, forcing conservative serialization that reduces parallel performance.\"},{\"question\":\"How does the proposed method perform memory conflict detection at the LLVM IR level?\",\"answer\":\"It extracts flat arithmetic expressions from getelementptr instructions and models memory banks as spatial predicates, turning structural collisions into spatial contradictions checked by SMT.\"},{\"question\":\"What is the role of Separation Logic in ensuring safety for concurrent memory accesses?\",\"answer\":\"Separation logic’s separating conjunction encodes disjointness, and the Conflict-Free Unrolling condition triggers contradictions when concurrent operations target the same memory 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do conventional polyhedral frameworks struggle with non-affine index arithmetic in HLS scheduling?","Question",{"text":75,"@type":76},"They systematically over-approximate non-linear transformations, forcing conservative serialization that reduces parallel performance.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"How does the proposed method perform memory conflict detection at the LLVM IR level?",{"text":80,"@type":76},"It extracts flat arithmetic expressions from getelementptr instructions and models memory banks as spatial predicates, turning structural collisions into spatial contradictions checked by SMT.",{"name":82,"@type":73,"acceptedAnswer":83},"What is the role of Separation Logic in ensuring safety for concurrent memory accesses?",{"text":84,"@type":76},"Separation logic’s separating conjunction encodes disjointness, and the Conflict-Free Unrolling condition triggers contradictions when concurrent operations target the same memory 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