[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-673078-105":59,"doc-detail-673078-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","processor-system-reset-module-logicore-ip-product-guide-v50","Processor System Reset Module - LogiCORE IP Product Guide - v5.0","","The LogiCORE IP Processor System Reset Module core delivers customized reset control for a complete processor system, including the processor, interconnect, and peripherals. It enables design-specific behavior through configurable parameters that select reset input activity levels (active-High/active-Low), minimum pulse width recognition, DCM Locked handling, and Power On Reset generation. The module sequences resets so interconnect and bus structures return first, peripherals follow after a fixed clock delay, and the MicroBlaze processor asserts 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peripherals.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},673078,1793619895,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":14,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":139,"language":140,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":141,"faqs":142,"seo_title":143,"seo_description":67,"update_tm":129,"read_time":144},1099529839121,"https://ap-avatar.wpscdn.com/davatar_994ba38a5ba835b3df7d355c54d3ed8d","Processor System Reset Module v5.0  \nLogiCORE IP Product Guide  \nPG164 November 18, 2015  \nTable of Contents  \nIP Facts  \nChapter 1: Overview  \nFeature Summary.................................................................. 5  \nLicensing and Ordering Information ................................................... 6  \nChapter 2: Product Specification Processor System Reset Module Circuit Description...................................... 7  \nPerformance ..................................................................... 10  \nResource Utilization ............................................................... 11  \nPort Descriptions ................................................................. 13  \nChapter 3: Designing with the Core Clocking......................................................................... 14  \nResets .......................................................................... 14  \nChapter 4: Customizing and Generating the Core Vivado Integrated Design Environment ............................................... 15  \nOutput Generation................................................................ 17  \nChapter 5: Constraining the Core  \nChapter 6: Simulation  \nChapter 7: Synthesis and Implementation  \nChapter 8: Example Design Implementing the Example Design ................................................... 22  \nSimulating the Example Design...................................................... 24  \nChapter 9: Test Bench  \nAppendix A: Migrating and Upgrading Migrating to the Vivado Design Suite ................................................. 27  \nProcessor System Reset Module v5.0  [www.xilinx.com](www.xilinx.com)[ ](www.xilinx.com)PG164 November 18, 2015  \nSend Feedback  \n2  \nUpgrading in the Vivado Design Suite ................................................ 27  \nAppendix B: Debugging  \n[Finding Help on Xilinx.com ......................................................... 28](Finding Help on Xilinx.com ......................................................... 28)  \n[Debug Tools ..................................................................... 30](Debug Tools ..................................................................... 30)  \n[Debugging General IP Behavior ..................................................... 30](Debugging General IP Behavior ..................................................... 30)  \nAppendix C: Additional Resources Xilinx Resources .................................................................. 32  \nReferences ...................................................................... 32  \nRevision History .................................................................. 33  \nNotice of Disclaimer............................................................... 33  \nProcessor System Reset Module v5.0  [www.xilinx.com](www.xilinx.com)[ ](www.xilinx.com)PG164 November 18, 2015  \nSend Feedback  \n3  \n\n| | | | IP Facts |\n| --- | --- | --- | --- |\n\nIntroduction  \nThe Xilinx LogiCORE™ IP Processor System Reset Module core provides customized resets for an entire processor system, including the processor, the interconnect and peripherals. The core allows customers to tailor their designs to suit their application by setting certain parameters to enable/disable features. The features of designs are discussed in the Design Parameters section.  \nFeatures  \n• Supports asynchronous external reset input which is synchronized with clock  \n• Both the external and auxiliary reset inputs are selectable as active-High or active-Low  \n• Selectable minimum pulse width for reset inputs to be recognized  \n• DCM Locked input  \n• Power On Reset generation  \n• Parameterized active-Low reset signal generation for core and for interconnect  \n• Sequencing of reset signals coming out of reset:  \na. Bus structures come out of reset (Interconnect and bridge)  \nb. Peripherals come out of reset 16 clock cycles later (UART, SPI, IIC)  \nc. The MicroBlaze™ processor comes out of reset 16 clock cycles after ","cbCaikw38ou4zxNn","https://ap.wps.com/l/cbCaikw38ou4zxNn","pdf",645316,33,"English","# IP Facts\n## Introduction\n## Features\n## Core Specifics\n# Chapter 1: Overview\n## Feature Summary","[{\"question\":\"What systems does the Processor System Reset Module reset control cover?\",\"answer\":\"It provides customized resets for an entire processor system, including the processor, the interconnect, and peripherals.\"},{\"question\":\"Which reset behaviors can be configured for the external and auxiliary reset inputs?\",\"answer\":\"Both external and auxiliary reset inputs are selectable as active-High or active-Low, and a selectable minimum pulse width can be set to ensure reset recognition.\"},{\"question\":\"How does the core sequence resets during startup?\",\"answer\":\"Bus structures come out of reset first, peripherals follow 16 clock cycles later, and the MicroBlaze processor comes out of reset 16 clock cycles after the peripherals.\"}]","Processor System Reset Module - LogiCORE IP Product Guide - v5.0 | PDF",83]