[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-118064-en":3,"doc-seo-118064-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},118064,549758252649,"Ivy","https://ap-avatar.wpscdn.com/avatar/8000253669c5317157?_k=1778319167496531819",8,"Research & Report","Physical Design Methods and Research Infrastructure for Machine Learning Accelerators","This dissertation investigates physical design methods and research infrastructure tailored to machine learning accelerators, addressing new design challenges driven by their large scale, novel dataflow/datapath structures, and the need for fast prototyping. It develops supervised and embedding-based techniques for hypergraph partitioning, including SpecPart and K-SpecPart, and introduces an open-source constraints-driven multi-tool for VLSI physical design. The work further proposes modern macro placement approaches for complex IP blocks and a GPU-accelerated analytical global placement framework for machine learning accelerators.","UC San Diego  \nUC San Diego Electronic Theses and Dissertations  \nTitle  \nPhysical Design Methods and Research Infrastructure for Machine Learning Accelerators  \nPermalink  \n[https://escholarship.org/uc/item/82s1730r](https://escholarship.org/uc/item/82s1730r)  \nAuthor  \nWang, Zhiang  \nPublication Date  \n2024  \nPeer reviewed|Thesis/dissertation  \n[eScholarship.org](eScholarship.org) Powered by the California Digital Library  \nUniversity of California  \nUNIVERSITY OF CALIFORNIA SAN DIEGO  \nPhysical Design Methods and Research Infrastructure for Machine Learning Accelerators  \nA dissertation submitted in partial satisfaction of the  \nrequirements for the degree  \nDoctor of Philosophy  \nin  \nElectrical Engineering (Computer Engineering)  \nby  \nZhiang Wang  \nCommittee in charge:  \nProfessor Andrew B. Kahng, Chair  \nProfessor Chung-Kuan Cheng  \nProfessor Bill Lin  \nProfessor David Z. Pan  \nProfessor Yusu Wang  \nCopyright Zhiang Wang, 2024 All rights reserved.  \nThe dissertation of Zhiang Wang is approved, and it is acceptable in quality and form for publication on microfilm and electronically.  \nUniversity of California San Diego  \n2024  \nDEDICATION  \nTo my family.  \nTABLE OF CONTENTS  \nDissertation Approval Page .................................................... iii  \nDedication .................................................................. iv  \nTable of Contents ............................................................ v  \nList of Figures ............................................................... vii  \nList of Tables ................................................................ xi  \nAcknowledgments ............................................................ xiv  \nVita ........................................................................ xvi  \nAbstract of the Dissertation .................................................... xviii  \nChapter 1 Introduction ..................................................... 1  \n1.1 New Challenges in Physical Design ..................................... 2  \n1.1.1 Large Scale of Machine Learning Accelerators ..................... 3  \n1.1.2 Novel Dataflow and Datapath Structures ........................... 4  \n1.1.3 Demand for Fast Prototyping .................................... 6  \n1.2 This Thesis .......................................................... 8  \nChapter 2 Partitioning in VLSI Physical Design ................................ 13  \n2.1 SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement .................................................... 14  \n2.1.1 Preliminaries .................................................. 16  \n2.1.2 SpecPart: An Overview ......................................... 20  \n2.1.3 The ISSHP Algorithm .......................................... 21  \n2.1.4 Experimental Validation ........................................ 31  \n2.1.5 Conclusion and Future Directions ................................ 36  \n2.2 K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning ............................................... 41  \n2.2.1 Preliminaries .................................................. 43  \n2.2.2 The K-SpecPart Framework ..................................... 44  \n2.2.3 Supervised Vertex Embedding ................................... 47  \n2.2.4 Extracting Solutions from Embeddings ............................ 50  \n2.2.5 Solution Ensembling via Cut Overlay ............................. 52  \n2.2.6 Experimental Validation ........................................ 53  \n2.2.7 Conclusion and Future Directions ................................ 60  \n2.3 An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design ...................................................... 76  \n2.3.1 Related Work ................................................. 77  \n2.3.2 Problem Formulation ........................................... 79  \n2.3.3 Our Approach .........................","cbCainMSfF283EEA","https://ap.wps.com/l/cbCainMSfF283EEA","pdf",36545941,1,244,"English","en",105,"# Chapter 1 Introduction\n## 1.1 New Challenges in Physical Design\n## 1.2 This Thesis\n# Chapter 2 Partitioning in VLSI Physical Design\n## 2.1 SpecPart\n## 2.2 K-SpecPart\n## 2.3 Open-Source Constraints-Driven General Partitioning Multi-Tool\n# Chapter 3 Modern Macro Placement for Large-Scale Complex IP Blocks\n## 3.1 RTL-MP\n## 3.2 Hier-RTLMP\n# Chapter 4 GPU-Accelerated Global Placer for Machine Learning Accelerators\n## 4.1 DG-RePlAce","[{\"question\":\"What design challenges motivate this dissertation on machine learning accelerators?\",\"answer\":\"The dissertation targets challenges from the large scale of machine learning accelerators, novel dataflow and datapath structures, and the demand for fast prototyping.\"},{\"question\":\"How does the dissertation improve hypergraph partitioning for VLSI physical design?\",\"answer\":\"It proposes supervised spectral and embedding-based frameworks, including SpecPart and K-SpecPart, and uses approaches such as solution extraction and cut overlay with experimental validation.\"},{\"question\":\"What placement methods and infrastructure are proposed for large-scale designs?\",\"answer\":\"The dissertation introduces modern macro placement methods for complex IP blocks (RTL-MP and Hier-RTLMP) and a GPU-accelerated analytical global placement framework for machine learning accelerators (DG-RePlAce).\"}]","Physical Design Methods and Research Infrastructure for Machine Learning Accelerators | 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