[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-664009-105":59,"doc-detail-664009-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","pcb-land-pattern-design-and-surface-mount-guidelines-for-qfn-packages-renesas-tb389-rev803","PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages - Renesas TB389 Rev.8.03","","Renesas’ Quad Flat No Lead (QFN) technical brief provides general guidance for designing PCB land patterns and developing surface-mount soldering processes for the QFN family and its thinner variants (TQFN/UTQFN/XQFN) as well as dual-sided types (DFN/TDFN/UTDFN/XDFN). It covers package outline references, land and thermal design, stencil and solder mask recommendations, reflow and solder paste considerations, solder joint criteria, maximum downward force, and detailed rework procedures, emphasizing reliability and thermal performance.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/pcb-land-pattern-design-and-surface-mount-guidelines-for-qfn-packages-renesas-tb389-rev803/664009/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/pcb-land-pattern-design-and-surface-mount-guidelines-for-qfn-packages-renesas-tb389-rev803/664009.png","ImageObject",300,407,{"name":92,"@type":93},"8796093062539","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-30","2026-10-29",true,{"@type":102,"interactionType":103,"userInteractionCount":39},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What is the purpose of the PCB land pattern and surface-mount guidelines for QFN packages?","Question",{"text":112,"@type":113},"The document provides general guidelines to help develop land pattern layouts and solder mounting processes for QFN packages, supporting good long-term solder joint reliability and thermal/electrical performance.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"Which standards are referenced for QFN package outline drawings?",{"text":117,"@type":113},"For QFNs, the JEDEC MO-220 outline series generally applies. Individual Renesas product datasheets reference the appropriate Renesas package outline drawings and compliance to applicable industry standard outlines.",{"name":119,"@type":110,"acceptedAnswer":120},"How should the thermal land and thermal vias be designed for the exposed die pad?",{"text":121,"@type":113},"The thermal land should match 1:1 with the package exposed die pad, and a grid of 1.0mm to 1.2mm pitch thermal vias should be placed under it to connect to buried copper plane(s) for vertical heat escape and heat spreading.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},664009,1793236367,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":66,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":133,"file_id":134,"file_url":135,"file_type":136,"file_size":137,"view_count":39,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":138,"language":139,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":67,"update_tm":129,"read_time":36},8796093062539,"Technical Brief  \nPCB Land Pattern Design and Surface Mount Guidelines for QFN Packages  \nRenesas’Quad Flat No Lead (QFN) package family offering is a relatively new packaging concept that is currently experiencing rapid growth. This package family includes the general version, QFN, as well as thinner versions such as TQFN, UTQFN, and XQFN. The family encompasses lead pitches of 0.4mm and above. A sub-set of the Quad Flat No Lead is the Dual sided type (leads on only 2 of the 4 sides) which includes versions such as the DFN, TDFN, UTDFN, and XDFN. Within this document, the term QFN represents all family options. This family offers a variety of benefits including reduced lead inductance, a small sized near chip scale footprint, thin profile and low weight. It also uses perimeter I/O pads to ease PCB trace routing, and the exposed copper die-pad technology offers good thermal and electrical performance. These features make the QFN an ideal choice for many new applications where size, weight, and thermal and electrical performance are important.  \nThere are general industry references, such as IPC-SM-782, for printed circuit board (PCB) land pattern design. But because the QFN package style is relatively new, such industry guidelines for it are still in development. This Tech Brief helps by providing general guidelines for use in developing land pattern layouts and solder mounting processes.  \nFigure 1 . QFN PACKAGES  \nIt should be emphasized that these guidelines are general in nature and should only be considered a starting point in this effort. The user must apply their actual experiences and development efforts to optimize designs and processes for their manufacturing practices and the needs of varying end-use applications.  \nTB389 Rev.8.03 Mar 7, 2024  \nPage 1  \n© 2001-2024 Renesas Electronics  \nContents  \n1. QFN Package Outline Drawings ......................................................... 3  \n2. General Design Guidelines ............................................................. 3  \n3. Land Pattern Guidelines ............................................................... 3  \n3.1 Peripheral I/O Lands .............................................................. 3  \n3.2 PCB Thermal Land ............................................................... 3  \n3.3 Thermal Vias .................................................................... 4  \n4. Solder Mask Design .................................................................. 4  \n5. Stencil Guidelines .................................................................... 4  \n5.1 Stencil Design for I/O Lands ........................................................ 4  \n5.2 Stencil Design for Thermal Land ..................................................... 5  \n5.3 Stencil Type and Thickness ......................................................... 5  \n6. Solder Paste and Reflow Profile ........................................................ 5  \n7. Solder Joint Criteria .................................................................. 7  \n8. Maximum Downward Force ............................................................ 8  \n9. Rework Guidelines ................................................................... 8  \n9.1 Bake .......................................................................... 8  \n9.2 Component Removal .............................................................. 8  \n9.3 Site Redress ................................................................... 11  \n9.4 Solder Paste Printing ............................................................. 11  \n9.5 Component Placement and Reflow .................................................. 11  \n9.6 Manual Alternative to Solder Paste Printing/Component Placement and Reflow ............... 12  \n10. Revision History .................................................................... 15  \nTB389 Rev.8.03 Mar 7, 2024  \nPage 2  \n1. QFN Package Outline Drawings  \nRenesas’individual product datasheets refe","cbCaifg1i45EDUCw","https://ap.wps.com/l/cbCaifg1i45EDUCw","pdf",1231122,16,"English","# Contents\n## 1. QFN Package Outline Drawings\n## 2. General Design Guidelines\n## 3. Land Pattern Guidelines\n### 3.1 Peripheral I/O Lands\n### 3.2 PCB Thermal Land\n### 3.3 Thermal Vias\n## 4. Solder Mask Design\n## 5. Stencil Guidelines\n### 5.1 Stencil Design for I/O Lands\n### 5.2 Stencil Design for Thermal Land\n### 5.3 Stencil Type and Thickness\n## 6. Solder Paste and Reflow Profile\n## 7. Solder Joint Criteria\n## 8. Maximum Downward Force\n## 9. Rework Guidelines\n### 9.1 Bake\n### 9.2 Component Removal\n### 9.3 Site Redress\n### 9.4 Solder Paste Printing\n### 9.5 Component Placement and Reflow\n### 9.6 Manual Alternative to Solder Paste Printing/Component Placement and Reflow\n## 10. Revision History","[{\"question\":\"What is the purpose of the PCB land pattern and surface-mount guidelines for QFN packages?\",\"answer\":\"The document provides general guidelines to help develop land pattern layouts and solder mounting processes for QFN packages, supporting good long-term solder joint reliability and thermal/electrical performance.\"},{\"question\":\"Which standards are referenced for QFN package outline drawings?\",\"answer\":\"For QFNs, the JEDEC MO-220 outline series generally applies. Individual Renesas product datasheets reference the appropriate Renesas package outline drawings and compliance to applicable industry standard outlines.\"},{\"question\":\"How should the thermal land and thermal vias be designed for the exposed die pad?\",\"answer\":\"The thermal land should match 1:1 with the package exposed die pad, and a grid of 1.0mm to 1.2mm pitch thermal vias should be placed under it to connect to buried copper plane(s) for vertical heat escape and heat spreading.\"}]","PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages - Renesas TB389 Rev.8.03 | PDF"]